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User's Manual
A2 Processor
14.5.17 DBCR1 - Debug Control Register 1
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits
Field Name
32:33
IAC1US
34:35
IAC1ER
36:37
IAC2US
38:39
IAC2ER
40
///
41
IAC12M
42:47
///
48:49
IAC3US
50:51
IAC3ER
Alphabetical Register Listing
Page 560 of 897
DBCR1
309
0x0000000000000000
N
Initial
Value
0b00
Instruction Address Compare 1 User/Supervisor Mode
00
Enabled: IAC1 debug events can occur.
01
Reserved.
10
Enabled PR0: IAC1 debug events can occur only if MSR[PR] = 0.
11
Enabled PR1: IAC1 debug events can occur only if MSR[PR] = 1.
0b00
Instruction Address Compare 1 Effective/Real Mode
00
Effective: IAC1 debug events are based on effective addresses.
01
Not implemented.
10
Effective IS0: IAC1 debug events are based on effective addresses and if
MSR[IS] = 0.
11
Effective IS1: IAC1 debug events are based on effective addresses and if
MSR[IS] = 1.
0b00
Instruction Address Compare 2 User/Supervisor Mode
00
Enabled: IAC2 debug events can occur.
01
Reserved.
10
Enabled PR0: IAC2 debug events can occur only if MSR[PR] = 0.
11
Enabled PR1: IAC2 debug events can occur only if MSR[PR] = 1.
0b00
Instruction Address Compare 2 Effective/Real Mode
00
Effective: IAC2 debug events are based on effective addresses.
01
Not implemented.
10
Effective IS0: IAC2 debug events are based on effective addresses and if
MSR[IS] = 0.
11
Effective IS1: IAC2 debug events are based on effective addresses and if
MSR[IS] = 1.
0b0
Reserved
0b0
Instruction Address Compare 1/2 Mode
0
Exact address compare.
1
Address bit match.
0x0
Reserved
0b00
Instruction Address Compare 3 User/Supervisor Mode
00
Enabled: IAC3 debug events can occur.
01
Reserved.
10
Enabled PR0: IAC3 debug events can occur only if MSR[PR] = 0.
11
Enabled PR1: IAC3 debug events can occur only if MSR[PR] = 1.
0b00
Instruction Address Compare 3 Effective/Real Mode
00
Effective: IAC3 debug events are based on effective addresses.
01
Not Implemented.
10
Effective IS0: IAC3 debug events are based on effective addresses and if
MSR[IS] = 0.
11
Effective IS1: IAC3 debug events are based on effective addresses and if
MSR[IS] = 1.
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
Hypv
Hypv
Y
func
Version 1.3
October 23, 2012
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