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Machine State Register (MSR)
7.6.10 Auxiliary Processor Unavailable Interrupt
An auxiliary processor unavailable interrupt occurs when no higher priority exception exists, an attempt is
made to execute an auxiliary processor instruction that is not implemented within the A2 core but which is
recognized by an attached auxiliary processor, and auxiliary processor instruction processing is not enabled
(CCR2[AP] = 0).
When an auxiliary processor unavailable interrupt occurs, the processor suppresses the execution of the
instruction causing the auxiliary processor unavailable exception, the interrupt processing registers are
updated as indicated in the following list (all registers not listed are unchanged), and instruction execution
resumes at address IVPR[IVP] || 0x140.
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
7.6.11 Decrementer Interrupt
A decrementer interrupt occurs when no higher priority exception exists, a decrementer exception exists
(TSR[DIS] = 1), and the interrupt is enabled (TCR[DIE] = 1 and (MSR[EE] = 1 or MSR[GS] = 1)). See Timer
Facilities on page 387 for more information about decrementer exceptions.
Note: MSR[EE] also enables other interrupts. See Table 7-3 Interrupt and Exception Types on page 323.
When a decrementer interrupt occurs, the interrupt processing registers are updated as indicated in the
following list (all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP]
|| 0x160.
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Version 1.3
October 23, 2012
CM set to EPCR[GICM] if the interrupt is directed to guest state;
otherwise, it is set to EPCR[ICM].
GS is left unchanged if the interrupt is directed to guest state; other-
wise, it is set to zero.
UCLE is left unchanged if the interrupt is directed to the guest state
and MSRP[UCLEP] = 1; otherwise, it is set to 0.
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Bits in the MSR corresponding to set bits in the MSRP register are
left unchanged.
Set to the effective address of the instruction causing the auxiliary
processor unavailable interrupt.
Set to the contents of the MSR at the time of the interrupt.
CM set to EPCR[ICM].
CE, ME, DE, ICM Unchanged.
All other MSR bits are set to 0.
Set to the effective address of the next instruction to be executed.
Set to the contents of the MSR at the time of the interrupt.
User's Manual
A2 Processor
CPU Interrupts and Exceptions
Page 343 of 864
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