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User's Manual
A2 Processor
• CT = 0 indicates L1 only. Note that icbtls CT = 0 is treated the same as icbt CT = 0 because instruction
cache locking/unlocking is not supported.
• CT = 2 indicates L2 only. The cache line is not placed in the L1 if it does not exist and is not locked in the
L1.
For unlocking instructions:
• CT = 0 indicates L1 only. Note that icblc CT = 0 is not sent to the L2.
• CT = 2 indicates L2 only.
Lock instructions are treated as loads when translated by the data TLB, and they cause exceptions when
data TLB errors or data storage interrupts occur.
The user-mode cache lock enable bit, MSR[UCLE], is used to restrict user-mode cache line locking by the
operating system. If MSR[UCLE] = 0, any cache lock instruction executed in user mode (MSR[PR] = 1)
causes a cache-locking DSI exception and sets ESR[DLK]. This allows the operating system to manage and
track the locking and unlocking of cache lines by user-mode tasks. If MSR[UCLE] is set to 1, the cache-
locking instructions can be executed in user mode and do not cause a DSI for cache locking. However, they
can still cause a DSI for access violations.
XUCR0[WLK] = 0: If all of the ways are locked in a cache set due to line locking, an attempt to lock another
line in that set results in an overlocking situation. The new line is not placed in the cache, and the data cache
overlock bit XUCR0[CLO] is set. This does not cause an exception condition.
XUCR0[WLK] = 1: If all of the ways are locked in a cache set with the combination of line locking for that
cache set and way locking via the RMT table; an attempt to bring in a new line, via a data cache load miss, to
that cache set results in an overlocking situation. The new line is not placed in the cache, and the data cache
overlock bit XUCR0[CLO] is set. This does not cause an exception condition.
The following cases cause an attempted lock or unlock to fail:
• The target address is marked caching-inhibited.
• The L1 D-cache is disabled, and the CT operand of the data cache locking instruction = 0.
• The CT operand of the cache locking instruction is not equal to 0 or 2.
In these cases, the lock set instruction is treated as a no-op and the data cache unable-to-lock bit
XUCR0[CUL]) is set. This condition does not cause an exception.
It is acceptable to lock all ways of the data cache. A nonlocking line fill for a new address in a completely
locked data cache set is not put into the data cache.
Locking all ways in the L2 cache that might be shared by multiple A2 cores causes capacity evictions of
potentially locked lines. See the L2 User's Manual for a detailed description.
The cache-locking DSI handler must decide whether to lock a given cache line based on available cache
resources.
If the locking instruction is a set lock instruction, to lock the line, the handler should do the following:
1. Add the line address to its list of locked lines.
2. Execute the appropriate set lock instruction to lock the cache line.
3. Modify Save/Restore Register 0 (SRR0) to point to the instruction immediately after the locking instruc-
tion that caused the DSI.
Instruction and Data Caches
Page 180 of 864
Version 1.3
October 23, 2012
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