Virtual Address Formation; Address Space Identifier Convention - IBM A2 User Manual

User's Manual
A2 Processor

6.2.1 Virtual Address Formation

The first step in page identification is the expansion of the effective address into a virtual address. Again, the
effective address is the 64-bit address calculated by a load, store, or cache management instruction, or as
part of an instruction fetch. The virtual address is formed by prepending the effective address with a 1-bit
guest space identifier, an 8-bit logical partition identifier, a 1-bit address space identifier, and a 14-bit process
identifier. The resulting 88-bit value forms the virtual address, which is then compared to the virtual addresses
contained in the TLB entries (note that the "IND" bit, or indirect entry identifier, is not formally considered part
of the virtual address, although it does participate in entry identification and invalidation).
For instruction fetches, cache management operations, and for nonexternal PID storage accesses, these
parameters are obtained as follows. The guest space identifier is provided by MSR[GS]. The logical partition
identifier is provided by the Logical Partition ID (LPID) Register. The process identifier is contained in the
Process ID (PID) Register. The address space identifier is provided by MSR[IS] for instruction fetches and by
MSR[DS] for data storage accesses and cache management operations, including instruction cache manage-
ment operations.
For external PID type load and store accesses, these parameters are obtained from the External PID Load
Context (EPLC) or External PID Store Context (EPSC) Registers. The guest space identifier is provided by
the EPLC or EPSC[EGS] field. The logical partition identifier is provided by the EPLC or EPSC[ELPID] field.
The process identifier is provided by the EPLC or EPSC[EPID] field, and the address space identifier is
provided by EPLC or EPSC[EAS].
The tlbsx[.] instruction also forms a virtual address for software controlled searches of the TLB. This instruc-
tion calculates the effective address in the same manner as a data access instruction, but the guest space
and address space identifiers, as well as the process and logical partition identifiers, are provided by fields in
the MAS5 and MAS6 registers, rather than by the MSR, PID, and LPID registers (see TLB Search Instruction
(tlbsx[.]) on page 215 and Section 6.17 Storage Control Registers (Architected) on page 244).
Likewise, the eratsx[.] instruction also forms a virtual address for software controlled searches of the ERAT
structures. This instruction calculates the effective address in the same manner as a data access instruction,
but the guest space and address space identifiers, as well as the process identifier, are provided by fields in
the MMUCR0 register, rather than by the MSR and PID registers (see Section 12.3.3 ERAT Search Indexed
(eratsx[.]) on page 502 and Section 6.18 Storage Control Registers (Non-Architected) on page 277). Note
that the ERAT entries, unlike the TLB, do not contain the LPID value. Hence, the LPID does not participate in
the search of the ERAT.

6.2.2 Address Space Identifier Convention

The address space identifier differentiates between two distinct virtual address spaces, one generally associ-
ated with interrupt-handling and other system-level code and/or data, and the other generally associated with
application-level code and/or data.
Typically, user mode programs run with MSR[IS,DS] both set to 1, allowing access to application-level code
and data memory pages. Then, on an interrupt, MSR[IS,DS] are both automatically cleared to 0, so that the
interrupt handler code and data areas can be accessed using system-level TLB entries (that is, TLB entries
with the TS field = 0). It is also possible that an operating system could set up certain system-level code and
data areas (and corresponding TLB entries with the TS field = 1) in the application-level address space,
allowing user mode programs running with MSR[IS,DS] set to 1 to access them (system library routines, for
example, which can be shared by multiple user mode and/or supervisor mode programs). System-level code
that needs to use these areas must first set the corresponding MSR[IS,DS] field to use the application-level
TLB entries, or must set up alternative system-level TLB entries.
Version 1.3 Memory Management
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