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mechanism until an attempt is made to execute that instruction. An instruction TLB miss exception occurs
when an instruction fetch attempts to access a virtual address for which a valid TLB entry does not exist. See
Memory Management on page 185 for more information about the TLB.
When an instruction TLB error interrupt occurs, the processor suppresses the execution of the instruction
causing the instruction TLB miss exception, the interrupt processing registers are updated as indicated in the
following list (all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP]
|| 0x1E0.
If the interrupt is directed to guest state (EPCR[ITLBGS] = 1 and MSR[GS] = 1), GSRR0 and GSRR1 are set
in place of SRR0 and SRR1 respectively, and instruction execution resumes at address IVPR[IVP] || 0x1E0.
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
7.6.16 Vector Unavailable Interrupt
The vector unavailable interrupt occurs when no higher priority exception exists, an attempt is made to
execute a vector instruction that is recognized by an attached vector unit, and MSR[SPV] = 0.
When an vector unavailable interrupt occurs, the processor suppresses the execution of the instruction
causing the vector unavailable exception, the interrupt processing registers are updated as indicated in the
following list (all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP]
|| 0x200.
Save/Restore Register 0 (SRR0)Set to the effective address of the instruction causing the Auxiliary
Processor Unavailable interrupt.
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
Exception Syndrome Register (ESR)
7.6.17 Debug Interrupt
A debug interrupt occurs when no higher priority exception exists, a debug exception exists in the Debug
Status Register (DBSR), the processor is in internal debug mode (DBCR0[IDM] = 1), and debug interrupts
are enabled (MSR[DE] = 1). A debug exception occurs when a debug event causes a corresponding bit in the
DBSR to be set.
There are several types of debug exception, as follows:
Version 1.3
October 23, 2012
Set to the effective address of the instruction causing the instruction
TLB error interrupt.
Set to the contents of the MSR at the time of the interrupt.
CM set to EPCR[ICM].
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Set to the contents of the MSR at the time of the interrupt.
CM set to EPCR[ICM].
CE, ME, DE, ICM Unchanged.
All other MSR bits set to 0.
SPV Set to 1.
User's Manual
A2 Processor
CPU Interrupts and Exceptions
Page 347 of 864
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