IBM A2 User Manual page 506

User's Manual
A2 Processor
• The 3-bit SIZE value of the ERAT entry is equal to the 3-bit interpretation of the 4-bit RS
• The ExtClass value of the ERAT entry is 0.
This implementation requires the direct target page size to be specified by RS
target page size is used by the fully associative ERAT structures to minimize generous invalidations that
would otherwise occur when the full EPN is not transferred. If the direct page size specified by RS
supported by this implementation, an illegal instruction exception is generated.
When IS = '10', all ERAT entries on all processors in the same logical partition that have all of the following
properties are made invalid:
• The appropriate MMUCR1[I/DCTID] bit (for target I-ERAT or D-ERAT) is 0, and the 2-bit Class value of
the ERAT entry is equal to RS
• The ExtClass value of the ERAT entry is 0.
When IS = '01', all ERAT entries on all processors in the same logical partition that have all of the following
properties are made invalid:
• The 8-bit TID value of the ERAT entry is equal to MMUCR0
• Either the appropriate MMUCR1[I/DTTID] bit (for target I-ERAT or D-ERAT) is 0, or the 4-bit ThdID value
of the ERAT entry is equal to MMUCR0
• Either the appropriate MMUCR1[I/DCTID] bit (for target I-ERAT or D-ERAT) is 0, or the 2-bit Class value
of the ERAT entry is equal to MMUCR0
• The TID_NZ value of the ERAT entry is equal to or_reduce(MMUCR0
• The ExtClass value of the ERAT entry is 0.
When IS = '00', all ERAT entries on all processors in the same logical partition that have an ExtClass value of
0 are made invalid.
Implementation Dependent Instructions
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.
58:59
.
TID[52:55]
.
TID[50:51]
. For the IS = '11' form, the
60:63
.
TID[56:63]
).
TID[50:63]
.
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is not
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Version 1.3
October 23, 2012