Execution Unit Debug Register 0 (Xudbg0); Execution Unit Debug Register 1 (Xudbg1) - IBM A2 User Manual

User's Manual
A2 Processor

10.9.5 Execution Unit Debug Register 0 (XUDBG0)

Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
32:48 ///
49:51 WAY
52 ///
53:57 ROW
58:61 ///
62 EXEC NP
63 DONE

10.9.6 Execution Unit Debug Register 1 (XUDBG1)

Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
32:44 ///
45:48 WATCH
49:55 LRU
56:59 PARITY
60:61 ///
Debug Facilities
Page 440 of 864
XUDBG0
885
0x0000000000000000
Y
Initial
Value
0x0 Reserved
0b000 Data Cache Directory Way Select
Selects way for a data cache directory read.
0b0 Reserved
0x0 Data Cache Directory Row Select
Selects row for a data cache directory read.
0b0000 Reserved
0b0 Data Cache Directory Read Execute
1 Executes a data cache directory read.
0b0 Data Cache Directory Read Done
1 Indicates a data cache directory read operation has completed and the XUDBG1
and XUDBG2 registers are valid.
XUDBG1
886
0x0000000000000000
Y
Initial
Value
0x0 Reserved
0b0000 Data Cache Directory Watch Bits
0 Directory entry has no watch set.
1 Directory entry has watch set.
0x0 Data Cache Directory LRU
Indicates value of the LRU in the data cache directory.
0b0000 Data Cache Directory Parity
Indicates value of the parity bits in the data cache directory.
0b00 Reserved
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
NP
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
Hypv
Hypv
N
func
Hypv
None
N
func
Version 1.3
October 23, 2012