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User's Manual
A2 Processor
2.2.3 Byte Ordering
If scalars (individual data items and instructions) were indivisible, there would be no such concept as "byte
ordering." It is meaningless to consider the order of bits or groups of bits within the smallest addressable unit
of storage, because nothing can be observed about such order. Only when scalars, which the programmer
and processor regard as indivisible quantities, can comprise more than one addressable unit of storage does
the question of order arise.
For a machine in which the smallest addressable unit of storage is the 64-bit doubleword, there is no question
of the ordering of bytes within doublewords. All transfers of individual scalars between registers and storage
are of doublewords, and the address of the byte containing the high-order 8 bits of a scalar is no different
from the address of a byte containing any other part of the scalar.
For the Power ISA Architecture, as for most current computer architectures, the smallest addressable unit of
storage is the 8-bit byte. Many scalars are halfwords, words, or doublewords that consist of groups of bytes.
When a word-length scalar is moved from a register to storage, the scalar occupies 4 consecutive byte
addresses. It thus becomes meaningful to discuss the order of the byte addresses with respect to the value of
the scalar: which byte contains the highest-order 8 bits of the scalar, which byte contains the next-highest-
order 8 bits, and so on.
Given a scalar that contains multiple bytes, the choice of byte ordering is essentially arbitrary. There are 24
ways to specify the ordering of 4 bytes within a word, but only two of these orderings are sensible:
• The ordering that assigns the lowest address to the highest-order (left-most) 8 bits of the scalar, the next
sequential address to the next-highest-order 8 bits, and so on.
This ordering is called big endian because the "big end" (most-significant end) of the scalar, considered
as a binary number, comes first in storage. IBM RISC System/6000, IBM System/390®, and Motorola
680x0 are examples of computer architectures using this byte ordering.
• The ordering that assigns the lowest address to the lowest-order ("right-most") 8 bits of the scalar, the
next sequential address to the next-lowest-order 8 bits, and so on.
This ordering is called little endian because the "little end" (least-significant end) of the scalar, considered
as a binary number, comes first in storage. The Intel x86 is an example of a processor architecture using
this byte ordering.
Power ISA supports both big-endian and little-endian byte ordering, for both instruction and data storage
accesses. Which byte ordering is used is controlled on a memory page basis by the endian (E) storage
attribute, which is a field within the TLB entry for the page. The endian storage attribute is set to 0 for a big-
endian page and is set to 1 for a little-endian page. See Memory Management on page 185 for more informa-
tion about memory pages, the TLB, and storage attributes, including the endian storage attribute.
2.2.3.1 Structure Mapping Examples
The following C language structure,
comments show the value assumed to be in each structure element; these values show how the bytes
comprising each structure element are mapped into storage.
struct {
int a;
long long b;
int c;
char d[7];
CPU Programming Model
Page 66 of 864
s
, contains an assortment of scalars and a character string. The
/* 0x1112_1314 word */
/* 0x2122_2324_2526_2728 doubleword */
/* 0x3132_3334 word */
/* 'A','B','C','D','E','F','G' array of bytes */
Version 1.3
October 23, 2012
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