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15. SCOM Accessible Registers
The serial communications (SCOM) interface provides access to registers used for pervasive operations. A
SCOM satellite within the PC unit provides the external connections and address decode needed for
accessing these registers. All SCOM accessible registers reside within the PC unit. Access to other core
registers through the SCOM interface is enabled by the Ram Instruction, Ram Command, and Ram Data
Registers. These registers are used for debug access to core facilities and to enable "instruction stuffing" into
a stopped thread's pipeline.
15.1 Serial Communications (SCOM) Description
The SCOM interface is the primary method for pervasive access to A2 registers in the chip. This section
provides a brief introduction to SCOM as it relates to register access within the A2 core. An overview of the
SCOM components and connections is shown in Figure 15-1 on page 702.
Register accesses initiated by master devices (JTAG, POR engine, alter/display unit) go through the perva-
sive control bus (PCB) to the chiplet-level SCOM controller. Upper bits of the SCOM address determine the
destination ring number that the device uses for routing the packet and which SCOM2 satellite is selected.
The SCOM2 satellite completes the address decode and performs the read or write operation.
The external interface for the SCOM2 satellite is comprised of a 2-wire serial connection for data and control;
in addition, 4 bits are used for programming the satellite address. The serial interface is further described by
direction of data flow: DL (downlink from the controller to the SCOM2 satellite) and UL (uplink from the
SCOM2 satellite back to the controller). The following signals make up the SCOM2 interface to the A2 core:
DL-CCH (1 bit)
UL-CCH (1 bit)
DL-DCH (1 bit)
UL-DCH (1 bit)
Satellite ID (4 bits)
Figure 15-2 on page 702 shows the basic use of the SCOM2 interface signals during SCOM read and write
operations. The address information sent by the PCB to the controller consists of 13 bits and is broken up into
the following fields:
Ring Number (3 bits)
Satellite Number (4 bits)
Register Number (6 bits)
Version 1.3
October 23, 2012
Downlink control channel. Controls clock and power-gating and satellite reset.
Uplink control channel to the next SCOM2 satellite in the chain or the controller.
Downlink data channel. Carries the address and data packets.
Uplink data channel to the next SCOM2 satellite in the chain or the controller.
Core inputs tied high or low that set the satellite ID on its SCOM ring. Compared
against the SCOM address to select a device.
The controller uses this field to select the ring number for forwarding the packet.
Valid ring numbers for connecting to a SCOM2 satellite are rings 1 through 7
(0b001 through 0b111). The ring number field is stripped off the serial address
bits forwarded to the SCOM2 satellites on the DCH signal.
The SCOM2 satellite compares these bits against its own satellite ID and, on a
match, responds to the packet by decoding the remaining address bits.
Allows access of up to 64 registers from a single SCOM2 satellite.
User's Manual
A2 Processor
SCOM Accessible Registers
Page 701 of 864
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