Table of Contents
Advertisement
User's Manual
A2 Processor
8. FU Interrupts and Exceptions
An interrupt is the action in which the processor saves its old context (Machine State Register [MSR] and next
instruction address [NIA]) and begins execution at a predetermined interrupt-handler address, with a modified
MSR. Exceptions are the events that can cause the processor to take an interrupt, if the corresponding inter-
rupt type is enabled.
Exceptions can be generated by the execution of instructions, or by signals from devices external to the A2
processor core, the internal timer facilities, debug events, or error conditions.
8.1 Floating-Point Exceptions
Book III-E requires all synchronous (precise and imprecise) interrupts to be reported in program order, as
required by the sequential execution model. The only exception to this rule is the case of multiple synchro-
nous imprecise interrupts. Upon a synchronizing event, all previously executed instructions are required to
report any synchronous imprecise interrupt-generating exceptions, and the interrupt is then generated with all
of those exception types reported cumulatively in both the Exception Syndrome Register (ESR) and any
status registers associated with the particular exception type, such as the Floating-Point Status and Control
Register (FPSCR).
For any single instruction attempting to cause multiple exceptions for which the corresponding synchronous
interrupt types are enabled, this section defines the priority order in which the instruction is permitted to cause
a single enabled exception, thus generating a particular synchronous interrupt. This exception priority mecha-
nism, along with the requirement that synchronous interrupts must be generated in program order, guaran-
tees that only one of the synchronous interrupt types is considered at any given time. The exception priority
mechanism also prevents certain debug exceptions from existing in combination with certain other synchro-
nous interrupt-generating exceptions.
This section does not define the permitted setting of multiple exceptions for which the corresponding interrupt
types are disabled. The generation of exceptions for which the corresponding interrupt types are disabled has
no effect on the generation of other exceptions for which the corresponding interrupt types are enabled.
Conversely, if a particular exception for which the corresponding interrupt type is enabled is shown in the
following sections to be of a higher priority than another exception, it prevents the setting of that other excep-
tion, regardless of whether the corresponding interrupt type of the other exception is enabled or disabled.
Except as noted, only one of the exception types listed for a given instruction type can be generated at any
given time. The priority of the exception types is listed in subsequent sections ranging from highest to lowest,
within each instruction type.
Note: Some exception types can be mutually exclusive of each other and can otherwise be considered the
same priority. In such cases, the exceptions are listed in the order suggested by the sequential execution
model.
Computational instructions can cause exceptions. Aside from instructions that write the FPSCR, none of the
noncomputational instructions can cause a floating-point exception.
All exceptions are handled precisely. Because this can affect performance adversely, it is strongly recom-
mended that exceptions should be disabled when possible. This prevents the A2 core instruction stream from
waiting for the execution of long latency instructions, such as fdiv[s] and fsqrt[s].
Version 1.3
FU Interrupts and Exceptions
October 23, 2012
Page 371 of 864
Advertisement
Table of Contents
