Table 6-11. Summary Of Supported Is Field Values In Erativax - IBM A2 User Manual

User's Manual
A2 Processor
The erativax invalidation snoops from the bus contain a target LPID value. The handling of the invalidation
snoops based on this LPID value is dependent on the configured mode of the receiving core. While a hetero-
geneous MMU mode system is not envisioned (that is, one in which some cores are configured for MMU
mode, while others are configured as ERAT-only mode), it might be possible for some system configurations
and is therefore described.
When the receiving core is operating in MMU mode (CCR2[NOTLB] = 0), the MMUCR1[TLBI_REJ] bit
controls the behavior of the snoop handling hardware based on the LPID value. If MMUCR1[TLBI_REJ] = '0',
the MMU accepts all incoming invalidation snoop operations, regardless of the current LPIDR register
contents, and includes the incoming LPID snoop value in its TLB entry invalidation match criteria. There is no
rejection of the transaction by the MMU in this case, and a TLBI_COMPLETE is issued to the memory
subsystem after the TLB and ERAT copies have been invalidated. Conversely, when MMUCR1[TLBI_REJ] =
'1' and an incoming invalidation snoop operation is targeted for a different partition from that contained in the
local LPIDR register, the MMU issues an immediate rejection of the transaction to the memory subsystem,
and no TLBI_COMPLETE is issued.
When the receiving core is operating in ERAT-only mode (CCR2[NOTLB] = 1) and an incoming invalidation
snoop operation is targeted for a different partition from that contained in the local LPIDR register, the MMU
issues an immediate rejection of the transaction to the memory subsystem, and no TLBI_COMPLETE is
issued. If the incoming invalidation snoop LPID value matches the current value of the LPIDR[LPID] field,
there is no rejection of the transaction by the MMU, and a TLBI_COMPLETE is issued to the memory
subsystem after the appropriate ERAT entries have been invalidated.
For this discussion, the term "AS" refers to the current addressing space as determined by MSR[IS] for
instruction fetches and by MSR[DS] for data accesses. This implementation supports a 88-bit virtual address
(1-bit GS || 8-bit LPID || 1-bit AS || 14-bit PID || 64-bit EA). For the erativax instruction, the MMUCR0[TGS],
[TS], [TID], and the LPIDR[LPID] register fields (TGS || LPID || TS || TID) are concatenated with bits [0:(63-p)]
of the EA, where p = log
tected entry in an ERAT in the same logical partition with matching TGS, TS, TID, effective page number
(EPN), and page size, or conditionally matching only page class, or conditionally matching only page TID, or
conditionally all non-protected entries is invalidated. The IS (invalidation select) field controls this, and is
provided in RS[56:57] of the erativax instruction. Table 6-11 gives details of the implementation of the IS
field.

Table 6-11. Summary of Supported IS Field Values in ERATIVAX

MMU Mode IS Field
ERAT-only 00
ERAT-only 01
ERAT-only 10
ERAT-only 11
TLB mode -
Memory Management
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(page size), and are used to form the VPN to match. In other words, any nonpro-
2
Local/Global
Global INVAL_ALL
All nonprotected entries associated with the logical partition "lpid" are invalidated.
Global INVAL_TID
All nonprotected entries associated with logical partition "lpid" that match TID are invali-
dated.
Global INVAL_CLASS
All nonprotected entries associated with logical partition "lpid" that match CLASS are
invalidated.
Global The logic is as selective as possible when invalidating nonprotected entries associated
with logical partition "lpid". The invalidation match criteria is EPN[31:(63-p)], TGS, TS,
TID, and SIZE.
- Not supported; illegal instruction exception
Behavior
Version 1.3
October 23, 2012