Iudbg1 - Instruction Unit Debug Register 1 - IBM A2 User Manual

14.5.58 IUDBG1 - Instruction Unit Debug Register 1

Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
32:52 ///
53:55 LRU
56:59 PARITY
60 ENDIAN
61:62 ///
63 VALID
Version 1.3
October 23, 2012
IUDBG1
889
0x0000000000000000
Y
Initial
Value
0x0 Reserved
0b000 Instruction Cache Directory LRU
Indicates value of the LRU in the instruction cache directory.
0b0000 Instruction Cache Directory Parity
Indicates value of the parity bits in the instruction cache directory.
0b0 Instruction Cache Directory Endian
0 Big endian.
1 Little endian.
0b00 Reserved
0b0 Instruction Cache Directory Read Valid
0 Directory entry is not valid.
1 Directory entry is valid.
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
User's Manual
A2 Processor
Hypv
None
N
func
Alphabetical Register Listing
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