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User's Manual
A2 Processor
data is implemented on each debug multiplexer output, and on the input of the MMU's debug multiplexer. The
following table also shows the cycles of delay of each debug multiplexer component's output, relative to the
external trace trigger bus.
Ramp bus order
Ramp bus component
Stages behind output bus -9
For debug/trigger groups from one unit to be driven out on the external buses, all downstream debug multi-
plexer components must be set to pass through the input trace/trigger data from the previous multiplexer.
This is the default initialization value for the debug select registers.
C.3 Example Debug Multiplexer Configuration Settings
C.3.1 Multiplexer Configuration for Trace/Trigger Signals from a Single Unit
This example selects a set of debug/trigger groups from one unit and drives them out on the external trace
and trigger buses. For this example, the signals all come from IU1 debug group 6 and trigger group 3.
1. SCOM write 0x00000000_00000000 to XDSR1, XDSR2, and MPDSR.
Sets the debug/trigger group output selects for each downstream debug/trigger multiplexer to pass
through the input trace and trigger data.
2. SCOM write 0x00000000_C1FB0000 to IDSR.
• IDSR(32:34) = 110; selects debug group 6.
• IDSR(35:36) = 00; reserved.
• IDSR(37:38) = 00; debug data not rotated.
• IDSR(39:42) = 1111; IU debug data driven on debug multiplexer outputs.
• IDSR(43:44) = 11; selects trigger group 3.
• IDSR(45) = 0; trigger data not rotated.
• IDSR(46:47) = 11; IU trigger data driven on trigger multiplexer outputs.
C.3.2 Multiplexer Configuration for Trace/Trigger Signals from Multiple Units
This example selects debug/trigger data from both the AXU and XU1 debug multiplexers. The AXU debug
data is rotated so that bits 0 to 43 of debug group 1 are driven out on bits 44 to 87 of the debug bus. Likewise,
the AXU trigger data is rotated so that bits 0 to 5 of trigger group 2 are driven on bits 6 to 11 of the trigger bus.
The XU1 data is from debug group 5 and trigger group 0 and is not rotated.
1. SCOM write 0x00000000_00000000 to IDSR, XDSR2 and MPDSR.
Sets the debug/trigger group output selects for each downstream debug/trigger multiplexer to pass
through the input trace and trigger data.
2. SCOM write 0x00000000_44750000 to ABDSR.
• ABDSR(32:33) = 01; selects debug group 1.
• ABDSR(34:36) = 000; reserved.
• ABDSR(37:38) = 10; rotate bits 0 to 43 of debug group to bits 44 to 87 of the debug multiplexer out-
put.
Debug and Trigger Groups
Page 762 of 864
1
2
3
4
AXU
PC
IU1
IU2
-8
-7
-6
5
6
7
8
XU1
XU2
XU3
XU4
-5
-4
-3
-2
9
MMU
(The MMU multiplexer component output is
the external trace/trigger bus)
0
October 23, 2012
Version 1.3
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