IBM A2 User Manual page 14

User's Manual
A2 Processor
10.11 PC Configuration Register 0 (PCCR0) ...................................................................................... 444
10.12 Trace and Trigger Bus ............................................................................................................... 445
10.12.1 Trace and Trigger Bus Overview ..................................................................................... 445
10.12.2 Unit Level Trace and Trigger Bus Implementation ........................................................... 446
10.12.3 Debug Select Registers ................................................................................................... 447
11. Performance Events and Event Selection ........................................................... 449
11.1 Event Bus Overview .................................................................................................................... 449
11.2 A2 Core Event Bus and PC Unit Controls ................................................................................... 450
11.2.1 Enabling Performance Event and Trace Bus Latches ....................................................... 450
11.2.2 Performance Analysis Operating Modes ........................................................................... 450
11.2.3 Core Performance Event Selection to External Event Bus ................................................ 450
11.2.4 Core Event Select Register (CESR) .................................................................................. 452
11.3 Unit Level Performance Event Selection ..................................................................................... 454
11.3.1 Unit Event Multiplexer Component .................................................................................... 454
11.3.2 Performance Monitor Event Tags and Count Modes ......................................................... 456
11.3.3 Unit Performance Event Tables ......................................................................................... 457
11.4 Unit Performance Event Tables .................................................................................................. 458
11.4.1 FU Performance Events Table ........................................................................................... 458
11.4.2 IU Performance Events Table ............................................................................................ 458
11.4.3 XU Performance Events Table .......................................................................................... 460
11.4.4 LSU Performance Events Table ........................................................................................ 462
11.4.5 MMU Performance Events Table ....................................................................................... 465
11.5 Unit Event Select Registers ......................................................................................................... 466
11.5.1 FU Event Select Register (AESR) ..................................................................................... 466
11.5.2 IU Event Select Registers .................................................................................................. 468
11.5.3 XU Event Select Registers ................................................................................................. 470
11.5.4 LSU Event Select Registers ............................................................................................... 472
11.5.5 MMU Event Select Registers ............................................................................................. 474
11.6 A2 Support for Core Instruction Trace ......................................................................................... 476
11.6.1 Instruction Trace Mode Setup ............................................................................................ 476
11.6.2 Instruction Trace Record Data ........................................................................................... 476
11.6.3 Instruction Trace Record Formats and Ordering ............................................................... 477
11.6.4 Debug Bus Control When in Instruction Trace Mode ......................................................... 478
11.6.4.1 FU Trace Records ...................................................................................................... 479
11.6.4.2 XU Debug Bus Control ............................................................................................... 479
11.7 A2 Support for Instruction Sampling ............................................................................................ 479
12. Implementation Dependent Instructions ............................................................. 481
12.1 Miscellaneous .............................................................................................................................. 481
12.1.1 Attention (attn) ................................................................................................................... 481
12.2 TLB Management Instructions .................................................................................................... 482
12.2.1 TLB Read Entry (tlbre) ...................................................................................................... 482
12.2.2 TLB Write Entry (tlbwe) ..................................................................................................... 484
12.2.3 TLB Search Indexed (tlbsx[.]) ........................................................................................... 486
12.2.4 TLB Search and Reserve Indexed (tlbsrx.) ....................................................................... 488
12.2.5 TLB Invalidate Virtual Address Indexed (tlbivax) .............................................................. 490
12.2.6 TLB Invalidate Local Indexed (tlbilx) ................................................................................. 493
12.3 ERAT Management Instructions ................................................................................................. 496
Contents
Page 14 of 864
Version 1.3
October 23, 2012