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User's Manual
A2 Processor
endif
else // MSRP[UCLEP]=0 OR MSR[GS] = 0
if MSR[PR]=1 and MSR[UCLE]=0
Cache Locking Type Data Storage Interrupt
endif
end
2.12.2 Privileged SPRs
Most SPRs are privileged. The only defined nonprivileged SPRs are LR, CTR, XER, VRSAVE, SPRG3 - 7
(read access only), TBU (read access only), and TBL (read access only). The A2 core also treats all SPR
numbers with a 1 in bit 5 of the SPRN field as privileged, whether the particular SPR number is defined or not.
Thus, the core causes a privileged instruction exception type of program interrupt on any attempt to access
such an SPR number while in user mode. In addition, the core causes an illegal instruction exception type of
program interrupt on any attempt to access while in user mode an undefined SPR number with a 0 in SPRN
On the other hand, the result of attempting to access an undefined SPR number in supervisor mode is unde-
fined, regardless of the value in SPRN
2.13 Speculative Accesses
The Power ISA Architecture permits implementations to perform speculative accesses to memory, either for
instruction fetching or for data loads. A speculative access is defined as any access that is not required by the
sequential execution model (SEM).
For example, the A2 core speculatively prefetches instructions down the predicted path of a conditional
branch; if the branch is later determined to not go in the predicted direction, the fetching of the instructions
from the predicted path is not required by the SEM and thus is speculative. The A2 core always executes load
instructions in program order; load instructions are never speculative.
The architecture provides two mechanisms for protecting against errant accesses to such "non-well-behaved"
memory addresses. The first is the guarded (G) storage attribute, and protects against speculative data
accesses. The second is the execute permission mechanism, which protects against speculative instruction
fetches. Both of these mechanisms are described in Memory Management on page 185.
2.14 Synchronization
The A2 core supports the synchronization operations of the Power ISA architecture. There are three kinds of
synchronization defined by the architecture, each of which is described in the following sections.
2.14.1 Context Synchronization
The context of a program is the environment in which the program executes. For example, the mode (user or
supervisor) is part of the context, as are the address translation space and storage attributes of the memory
pages being accessed by the program. Context is controlled by the contents of certain registers and other
resources, such as the MSR and the translation lookaside buffer (TLB).
CPU Programming Model
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Version 1.3
October 23, 2012
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