Table of Contents
Advertisement
User's Manual
A2 Processor
Table C-13. XU Debug Mux3 Debug and Trigger Groups
Debug Group
1
0:7
8:12
13:13
14:17
18:21
22:22
23:23
24:31
32:32
33:43
44:63
64:64
65:65
66:66
67:67
68:68
69:69
70:70
71:71
72:72
73:73
74:76
77:77
78:79
80:80
81:82
83:87
2
0:0
1:1
2:7
8:12
13:21
22:43
44:44
45:45
46:49
50:50
51:56
57:57
58:58
59:59
60:60
61:61
62:62
63:63
64:64
65:65
66:66
67:69
70:75
76:80
81:81
82:87
Debug and Trigger Groups
Page 820 of 864
ex4_way_hit_q
ex4_p_addr_q(53:57)
ex4_congr_cl_q
binv4_ex4_xuop_upd_q
ex4_dir_access_op
ex4_p_addr(58:61)
ldq_rel_back_invalidated
ldq_rel_ci
ld_rel_val_l2
st_entry0_val_l2
ex4_p_addr(22:32)
ex4_p_addr(33:52)
load_cmd_count_l2(0)
store_cmd_count_l2(0)
ex2_is_mem_bar_op
ex3_l2_op_q
ex4_n_flush_rq_q
ldq_rel1_val
ldq_rel_mid_val
ldq_rel3_val
ldq_rel_retry_val
ldq_recirc_rel_val
ldq_rel_tag
ldq_rel_set_val
ldq_rel_ta_gpr(7:8)
ldq_rel_lock_en
ldq_rel_classid
rel_congr_cl_q
ex4_wayA_byp_ctrl_fxpipe
ex4_wayA_byp_ctrl_relpipe
ex4_wayA_val
ex4_congr_cl_q
ex4_p_addr
ex4_p_addr
ex4_way_hit_q(w)
binv4_ex4_xuop_upd_q
ex4_dir_access_op
binv_wayA_upd2_q
flush_wayA_data_q
ldq_rel1_val
ldq_rel_mid_val
ldq_rel3_val
ldq_rel_retry_val
ldq_recirc_rel_val
ldq_rel_set_val
rel_way_dwen(w)
rel_wayA_byp_ctrl_fxpipe
rel_wayA_byp_ctrl_relpipe
ldq_rel_back_invalidated
ldq_rel_tag
rel_wayA_val
rel_congr_cl_q
reload_wayA_upd2_q
reload_wayA_data_q
(Sheet 2 of 11)
Signal List
Version 1.3
October 23, 2012
Advertisement
Table of Contents
