IBM A2 User Manual page 331

Programming Note: The instruction cache management instructions icbi and icbt are treated as loads from
the addressed byte with respect to address translation and protection. These instruction cache management
instructions use MSR[DS] rather than MSR[IS] to determine translation for their target effective address. Sim-
ilarly, they use the read access control field (UR or SR) rather than the execute access control field (UX or
SX) of the TLB entry to determine whether a data storage exception should occur. Instruction storage excep-
tions and instruction TLB miss exceptions are associated with the fetching of instructions not with the execu-
tion of instructions. Data storage exceptions and data TLB miss exceptions are associated with the execution
of instruction cache management instructions, as well as with the execution of load, store, and data cache
management instructions.
Write Access Control Exception
A Write Access Control exception is caused by one of the following:
• While in user mode (MSR[PR] = 1), a store instruction attempts to access a location in storage that is not
enabled for write access in user mode (that is, the TLB entry associated with the memory page being
accessed has UW = 0).
• While in supervisor mode (MSR[PR] = 0), a store instruction attempts to access a location in storage that
is not enabled for write access in supervisor mode (that is, the TLB entry associated with the memory
page being accessed has SW = 0).
See Access Control Applied to Cache Management Instructions on page 194.
Byte Ordering Exception
A byte ordering exception occurs when a floating-point unit or auxiliary processor is attached to the A2 core,
and a floating-point or auxiliary processor load or store instruction attempts to access a memory page with a
byte order that is not supported by the attached processor. Whether or not a given load or store instruction
type is supported for a given byte order is dependent on the implementation of the floating-point or auxiliary
processor. All integer load and store instructions supported by the A2 core are supported for both big-endian
and little-endian memory pages.
Unavailable Coprocessor Type Exception
An unavailable coprocessor type exception will occur when following expression is true:
MSR[GS,PR] != 0b00 & (HACOP[CT] == 0 | (ACOP[CT] == 0 & MSR[PR] == 1))
Note that for icswepx, the following substitutions are made.
EPSC is used in place of MSR
EPR
EPSC is used in place of MSR
EGS
EPSC is used in place of MSR
EAS
See Section 12.5.2 Initiate Coprocessor Store Word External Process ID Indexed (icswepx[.]) on page 518.
Storage Synchronization Exception
A storage synchronization exception occurs when an attempt is made to execute a load and reserve or store
conditional instruction from or to a location that is write through required or caching inhibited.
Version 1.3
October 23, 2012
.
PR
.
GS
.
DS
User's Manual
A2 Processor
CPU Interrupts and Exceptions
Page 331 of 864