Table of Contents
Advertisement
User's Manual
A2 Processor
D.2.5 I-ERAT Misses
I-ERAT misses are similar to instruction cache misses. If no MMU is present, the miss proceeds like an
instruction through the pipeline and generate an instruction TLB miss exception at EX5. If the MMU is
present, the fetch address is reset back to the missing address, and the miss is sent to the MMU. When the
MMU responds with the translation, fetching is restarted. If the MMU is unable to provide a translation, an
instruction TLB miss exception is generated.
Like instruction cache misses, fetching can be resumed if a flush redirects fetch to a new address. Only one
I-ERAT miss can be outstanding per thread, so a second I-ERAT miss halts further progress until the first
I-ERAT miss comes back. Translations returned from the MMU are never discarded. They are always placed
in the I-ERAT.
D.2.6 Instruction Buffer Operation
There is one instruction buffer per thread situated in IU4. The instruction buffer holds eight instructions.
Instructions are not fetched unless there is guaranteed to be room for those instructions in the instruction
buffers. At IU0, a thread is not allowed to fetch more instructions if there are more than four instructions in the
instruction buffers, and there are never more than eight instructions for any one thread in stages IU1 to IU4.
Furthermore, each fetch is conservatively assumed to contain four instructions until it reaches the instruction
buffers. Hence, there are no more than two instruction fetches for any one thread in IU0 to IU4.
If the instruction buffers are empty, the first instruction bypasses the instruction buffer, proceeds directly to
decode, and is latched in IU5. Furthermore, there is a step-aside latch just before the IU5 latch that captures
one instruction when the IU5 latch is full. In addition, IU5 and IU6 can each contain one instruction per thread.
Hence, IU0 through IU6 can contain up to 11 instructions per thread.
To reduce the physical size of the instruction buffer, instructions use a truncated instruction address within
the instruction buffer. Instruction buffer entries only hold the low 22 bits of their address, and a single copy of
the upper bits is kept for all instructions in the buffer. If a fetch group from a different 16 MB region (that is,
different upper bits) reaches IU4, and the instruction buffers are not empty, then the fetch group is flushed
and refetched. This occurs until the instruction buffer empties, at which point the single copy of the upper bits
is changed to the new value. Hence, code sequences that cross 16 MB regions frequently should be avoided.
This is generally rare, and is therefore not a significant performance concern.
D.2.7 Branches and Branch Prediction
Branches are predicted and handled specially by the front end. Branch prediction consists of predicting the
direction (taken or not-taken) of the branch (taken or not-taken), and predicting the target address of the
branch (if taken). Figure D-3 illustrates the pipeline stages of the branch prediction function.
Instruction Execution Performance and Code Optimizations
Version 1.3
Page 838 of 864
October 23, 2012
Advertisement
Table of Contents
