Xucr2 - Execution Unit Configuration Register 2 - IBM A2 User Manual

User's Manual
A2 Processor

14.5.132 XUCR2 - Execution Unit Configuration Register 2

Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
32:39 RMT3
40:47 RMT2
48:55 RMT1
56:63 RMT0
Alphabetical Register Listing
Page 694 of 897
XUCR2
1016
0x00000000FFFFFFFF
Y
Initial
Value
0xFF L1 Replacement Management Table Entry 3
An RMT entry indicates which sets are eligible for replacement for a given data cache miss.
Each RMT entry is 8 bits, 1 bit corresponding to each way in the data cache.
The value of each bit indicates the following:
0 Way is not eligible for replacement.
1 Way is eligible for replacement.
0xFF L1 Replacement Management Table Entry 2
An RMT entry indicates which sets are eligible for replacement for a given data cache miss.
Each RMT entry is 8 bits, 1 bit corresponding to each way in the data cache.
The value of each bit indicates the following:
0 Way is not eligible for replacement.
1 Way is eligible for replacement.
0xFF L1 Replacement Management Table Entry 1
An RMT entry indicates which sets are eligible for replacement for a given data cache miss.
Each RMT entry is 8 bits, 1 bit corresponding to each way in the data cache.
The value of each bit indicates the following:
0 Way is not eligible for replacement.
1 Way is eligible for replacement.
0xFF L1 Replacement Management Table Entry 0
An RMT entry indicates which sets are eligible for replacement for a given data cache miss.
Each RMT entry is 8 bits, 1 bit corresponding to each way in the data cache.
The value of each bit indicates the following:
0 Way is not eligible for replacement.
1 Way is eligible for replacement.
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
Hypv
Hypv
N
func
Version 1.3
October 23, 2012