Lrat Configuration Register (Lratcfg) - IBM A2 User Manual

6.17.23 LRAT Configuration Register (LRATCFG)

The LRATCFG register is a read-only register that can be read into a GPR using mfspr. LRATCFG is used to
provide implementation-specific parameters regarding the LRAT to the hypervisor.
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
32:39 ASSOC
40:46 LASIZE
47:49 ///
50 LPID
51 ///
52:63 NENTRY
Version 1.3
October 23, 2012
LRATCFG
342
0x0000000000542008
Y
Initial
Value
0x0 Associativity
Indicates the number of ways that are implemented in this processor's LRAT. This field is
always set to '00000000' for this processor (fully associative LRAT).
0x2A Logical Address Size
Indicates the number of logical address (LA) bits that are implemented by this processor's
LRAT. This field is always set to '0101010' for this processor (42 bits).
0b000 Reserved
0b1 Logical Partition ID
Indicates that the LPID field is supported in the LRAT entries. This bit is always set to '1' for
this processor (the A2 does implement the LPID field in LRAT entries).
0b0 Reserved
0x8 Number of Entries
Indicates the number of entries that are implemented in this processor's LRAT. This field is
always set to '0000_0000_1000' for this processor (8 entries).
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
User's Manual
A2 Processor
Hypv
None
N
HM
func
Memory Management
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