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7.6.21 Guest Processor Doorbell Critical Interrupt
A guest processor doorbell critical interrupt occurs when no higher priority exception exists, a guest
processor doorbell critical exception is present, and the interrupt is enabled (MSR[GS] = 1 and MSR[CE] = 1).
Guest processor doorbell critical exceptions are generated when G_DBELL_CRIT messages (see
on page 357) are received and accepted by the processor.
Messages
Programming Note: Guest processor doorbell critical interrupts are used by the hypervisor to be notified
when the guest operating system has set MSR[CE] to 1. This allows the hypervisor to reflect critical class
interrupts to the guest at a time when the guest is ready to accept them (MSR[GS] = 1 and MSR[CE] = 1).
Programming Note: Guest processor doorbell critical interrupts and guest processor doorbell machine
check interrupts share the same IVO. Hypervisor software can differentiate between the two interrupts by
comparing whether CE or ME is set in CSRR1 and which interrupt class is to be reflected.
The interrupt processing registers are updated as indicated in the following list (all registers not listed are
unchanged) and instruction execution resumes at address IVPR[IVP] || 0x2E0.
Critical Save/Restore Register 0
(CSRR0)
Critical Save/Restore Register
1(CSRR1)
Machine State Register (MSR)
7.6.22 Guest Processor Doorbell Machine Check Interrupt
A guest processor doorbell machine check interrupt occurs when no higher priority exception exists, a guest
processor doorbell machine check exception is present, and the interrupt is enabled (MSR[GS] = 1 and
MSR[ME] = 1). Guest processor doorbell machine check exceptions are generated when G_DBELL_MC
messages (see Processor Messages on page 357) are received and accepted by the processor.
Programming Note: Guest processor doorbell machine check interrupts are used by the hypervisor to be
notified when the guest operating system has set MSR[ME] to 1. This allows the hypervisor to reflect machine
check class interrupts to the guest at a time when the guest is ready to accept them (MSR[GS] = 1 and
MSR[ME] = 1).
Programming Note: Guest processor doorbell critical interrupts and guest processor doorbell machine
check interrupts share the same IVO. Hypervisor software can differentiate between the two interrupts by
comparing whether CE or ME is set in CSRR1 and which interrupt class is to be reflected.
The interrupt processing registers are updated as indicated in the following list (all registers not listed are
unchanged) and instruction execution resumes at address IVPR[IVP] || 0x2E0.
Critical Save/Restore Register 0
(CSRR0)
Critical Save/Restore Register 1
(CSRR1)
Version 1.3
October 23, 2012
Set to the effective address of the next instruction to be executed.
Set to the contents of the MSR at the time of the interrupt.
CM set to EPCR[ICM].
ME unchanged.
All other defined MSR bits set to 0.
Set to the effective address of the next instruction to be executed.
Set to the contents of the MSR at the time of the interrupt.
User's Manual
A2 Processor
Processor
CPU Interrupts and Exceptions
Page 353 of 864
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