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Table 6-4. TLB Entry Fields
TLB
2
Bit
Field
1
Word
1
63
SR
(IND = 0)
RPN
52
(IND = 1)
Notes:
1. "TLB Word" for TLB entries refers to a functional grouping of the fields into page identification fields. For ERAT entries, this refers
to not only a functional grouping of fields, but also to the eratwe and eratre instruction word select (WS) field in 64-bit mode.
2. The "Bit" value in this column for TLB entries is for reference only, because these fields are transferred via tlbwe and tlbre instruc-
tions using the MMU Assist Registers (MAS), and the values in this column have no correlation to the bit numbering of the MAS
registers. For ERAT entries, the contents of this column indicate bit assignments in the source (RS) or target register (RT) for the
eratwe and eratre instructions respectively, in 64-bit mode.
3. The TID field contains 14 bits in TLB entries to fully and uniquely identify them with respect to the current process ID or the EPLC
or EPSC registers EPID values. For ERAT entries, only 8 bits of the TID field are implemented (for certain settings of the MMUCR1
register). When an ERAT miss is resolved from the TLB, the least significant 8 bits of the TLB TID field are stored into the ERAT
TID field. Supervisory software must guarantee uniqueness in the 8-bit TID field in the ERAT arrays to the extent necessary to
avoid multihit scenarios. Refer also to Section 6.18.2 Memory Management Unit Control Register 1 (MMUCR1) for a description of
the ICTID, ITTID, DCTID, and DTTID bits that affect this ERAT function.
4. The TLPID field does not exist in the ERAT entries (that is, ERAT entries are not tagged with the logical partition ID). Supervisory
software must guarantee that the ERAT entries contain translations from only one logical partition at a time.
5. These fields are implementation specific (nonarchitected) fields.
6. The IPROT bit exists in addition to the ExtClass field in TLB entries. ERAT entries are protected by using the ExtClass field only
(that is, the IPROT bit is not implemented in shadow copies).
7. The IND bit exists only in TLB entries; it is not implemented in ERAT shadow copies.
8. The Virtualization Fault (VF) bit exists only in TLB and D-ERAT entries; it is not implemented in the I-ERAT.
9. The function of these bits is dependent on if this entry is a direct (IND = 0) or indirect (IND = 1) type entry.
10. The SPSIZE
function for indirect (IND = 1) is treated as reserved for this implementation because sub-page sizes are a power of 4
4
subset of the architected power of 2 sub-page sizes.
11. This bit is used to store the RPN
field.
6.7 Effective to Real Address Translation Arrays
The A2 core implements two fully-associative effective to real address translation (ERAT) arrays also called
shadow TLB arrays): one for instruction fetches and one for data accesses. These arrays "shadow" the value
of a subset of the entries in the main, unified TLB (the UTLB in the context of this discussion). This subset of
TLB entries contained in the ERAT arrays is referred to as "TLB lookaside information" in the architecture.
The purpose of the ERAT arrays is to reduce the latency of the address translation operation and to avoid
contention for the UTLB array between instruction fetches and data accesses.
The instruction ERAT (I-ERAT) contains 16 entries, while the data ERAT (D-ERAT) contains 32 entries, and
all entries are shared between the four A2 processing threads. There is no latency associated with accessing
the ERAT arrays, and instruction execution continues in a pipelined fashion as long as the requested address
is found in the ERAT. If the requested address is not found in the ERAT, the instruction fetch or data storage
access is automatically stalled while the address is looked up in the UTLB. If the address is found in a direct
entry (IND = 0) residing in the UTLB, the penalty associated with the miss in the I-ERAT shadow array is 12
cycles, and the penalty associated with a miss in the D-ERAT shadow array is 19 cycles. If the address
Version 1.3
October 23, 2012
(Sheet 5 of 5)
Supervisor State Read Enable (IND = 0) or RPN
0
(IND = 0) Load operations and the dcbt, dcbtst, dcbst, dcbf, icbt, and icbi instructions
are not permitted from this page when MSR[PR] = 0 and will cause a read access control
exception. Except for the dcbt, dcbtst, and icbt instructions, a data storage interrupt will
occur.
1
(IND = 0) Load operations and the dcbt, dcbtst, dcbst, dcbf, icbt, and icbi instructions
are permitted from this page when MSR[PR] = 0.
LSB for indirect (IND = 1) entries in this implementation, which correlates to the MAS3
52
Description
9, 11
(IND = 1)
(1 bit)
52
User's Manual
A2 Processor
RPNL[52]
Memory Management
Page 203 of 864
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