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User's Manual
A2 Processor
the establishment and replacement of TLB entries by simply not using indirect entries (that is, by using only
direct IND = 0 entries). This gives system software significant flexibility in implementing a custom page
replacement strategy. For example, to reduce TLB thrashing or translation delays, software can reserve
several TLB entries for globally accessible static mappings. The instruction set provides several instructions
for managing TLB entries. These instructions are privileged, and the processor must be in supervisor state i
for them to be executed.
The first step in the address translation process is to expand the effective address into a virtual address. This
is done by taking the 64-bit effective address and prepending to it a 1-bit guest state (GS) identifier, an 8-bit
logical partition ID (LPID), a 1-bit address space (AS) identifier, and the 14-bit process identifier (PID). The
1-bit indirect entry (IND) identifier is not considered part of the virtual address. The LPID value is provided by
the LPIDR register, and the PID value is provided by the PID register (see Memory Management on
page 185). The GS and AS identifiers are provided by the Machine State Register (MSR, see CPU Interrupts
and Exceptions on page 293), which contains separate bits for the instruction fetch address space (MSR[IS])
and the data access address space (MSR[DS]). Together, the 64-bit effective address and the other identi-
fiers form an 88-bit virtual address. This 88-bit virtual address is then translated into the 42-bit real address
using the TLB.
The MMU divides the address space (whether effective, virtual, or real) into pages. Five direct (IND = 0) page
sizes (4 KB, 64 KB, 1 MB, 16 MB, 1 GB) are simultaneously supported, such that at any given time the TLB
can contain entries for any combination of page sizes. The MMU also supports two indirect (IND = 1) page
sizes (1 MB and 256 MB) with associated sub-page sizes (see Section 6.16 Hardware Page Table Walking
(Category E.PT)). For an address translation to occur, a valid direct entry for the page containing the virtual
address must be in the TLB. An attempt to access an address for which no TLB direct exists results in a
search for an indirect TLB entry to be used by the hardware page table walker. If neither a direct or indirect
entry exists, an instruction (for fetches) or data (for load/store accesses) TLB miss exception occurs.
To improve performance, both the instruction cache and the data cache maintain separate shadow TLBs
called ERATs. The ERATs contain only direct (IND = 0) type entries. The instruction ERAT (I-ERAT) contains
16 entries, while the data ERAT (D-ERAT) contains 32 entries. These ERAT arrays minimize TLB contention
between instruction fetch and data load/store operations. The instruction fetch and data access mechanisms
only access the main unified TLB when a miss occurs in the respective ERAT. Hardware manages the
replacement and invalidation of both the I-ERAT and D-ERAT; no system software action is required in MMU
mode. In ERAT-only mode, an attempt to access an address for which no ERAT entry exists causes an
instruction (for fetches) or data (for load/store accesses) TLB miss exception.
Each TLB entry provides separate user state and supervisor state read, write, and execute permission
controls for the memory page associated with the entry. If software attempts to access a page for which it
does not have the necessary permission, an instruction (for fetches) or data (for load/store accesses) storage
exception occurs.
Each TLB entry also provides a collection of storage attributes for the associated page. These attributes
control cache policy (such as cacheability and write-through as opposed to copy-back behavior), byte order
(big-endian as opposed to little-endian), and enabling of speculative access for the page. In addition, a set of
four, user-definable storage attributes are provided. These attributes can be used to control various system-
level behaviors.
Section 6 Memory Management describes the A2 core MMU functions in greater detail.
Version 1.3
Overview
October 23, 2012
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