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User's Manual
A2 Processor
12.2.4 TLB Search and Reserve Indexed (tlbsrx.)
Software can use the tlbsrx. instruction to search for entries in the local TLB and, as a side-affect, sets a
local TLB reservation for the associated virtual address.
Because the Embedded.Hypervisor category is supported, if guest execution of TLB management instruc-
tions is disabled (EPCR
tion is supervisor privileged. Because this instruction relies on the MAS Registers, execution of this
instruction in ERAT-only mode (CCR2[NOTLB] = 1) results in an illegal instruction exception. The instruction
format and details follow.
tlbsrx.
RA,RB
31
///
RA
0
6
11
if RA = 0 then b 0 else b (RA)
EA b + (RB)
EPN EA
0:51
pid MAS1
TID
as MAS1
TS
ind MAS1
IND
gs MAS5
SGS
lpid MAS5
SLPID
thread_num number of executing thread (0 to 3)
vpn gs || lpid || as || pid || EPN
1
TLB-RESERVATION
V
ind
TLB-RESERVATION
IND
gs
TLB-RESERVATION
GS
lpid
TLB-RESERVATION
LPID
as
TLB-RESERVATION
AS
pid
TLB-RESERVATION
PID
EPN
TLB-RESERVATION
EPN
Valid_matching_entry_exists 0
for each TLB entry
m ¬((1 << (2 X (entry
n 64-log
(page size in bytes)
2
if ((EA
& m) = (entry
0:51
(entry
= MAS5
TLPID
(entry
= MAS1
TID
(entry
= 0 | EPN
X
then
Valid_matching_entry_exists 1
exit for loop
if Valid_matching_entry_exists = 1 then
CR0 0b0010
else
CR0 0b0000
Implementation Dependent Instructions
Page 488 of 864
= 1), this instruction is embedded hypervisor privileged. Otherwise, this instruc-
DGTMI
RB
850
1
16
21
31
- 1))) - 1)
SIZE
& m)) &
EPN
| entry
SLPID
TLPID
| entry
= 0) & (entry
TID
TID
> entry
n:51
EPN[n:51]
Rc = 1
= 0) & (entry
= MAS5
TGS
= MAS1
) & (entry
TS
TS
) & (entry
(thread_num) = 1)
THDID
) &
SGS
= MAS1
) &
IND
IND
October 23, 2012
Version 1.3
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