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10. Debug Facilities
The debug facilities of the A2 core include support for several debug modes for debugging during hardware
and software development, as well as debug events that allow developers to control the debug process.
Debug registers control these debug modes and debug events. The debug registers can be accessed either
through software running on the processor or through the JTAG port via the SCOM interface of the A2 core.
Access to the debug facilities through the JTAG port is typically provided by a debug tool such as the RISC-
Watch development tool from IBM. A trace bus, which enables the tracing of code running in real time, is also
provided.
10.1 Implications of Hypervisor on Debug Controls
The Power ISA Embedded.Hypervisor category provides several controls that affect debug operation within
the A2 core. All debug events are dependent on the state of EPCR[DUVD] and MSR[GS] to determine if
debug events can occur when executing in the hypervisor state (MSR[GS,PR] = 00). When EPCR[DUVD] =
1, debug events are enabled for guest state (MSR[GS] = 1) operation only. This stops debug events intended
for code executing in the guest state from occurring when the hypervisor is active. Another control determines
if the MSR[DE] bit can be modified when executing in guest state. If MSRP[DEP] is set to 1, a guest state
write operation to MSR[DE] is ignored. See Section 14.5 on page 537 for detailed descriptions of the MSR,
MSRP, and EPCR registers.
DBSRWR is a hypervisor accessible debug register. It allows code executing in hypervisor state to set bits in
the DBSR. DBSRWR is bit-for-bit compatible with the DBSR register. When a 1 is written to DBSRWR, the
corresponding DBSR bit is set. The DBSRWR register is shown in Section 10.7.6 on page 423.
10.2 Support for Development Tools
The RISCWatch product from IBM is an example of a development tool that uses external debug mode,
debug events, and the JTAG interface to implement a hardware and software development tool. Registers in
the A2 core are not directly accessible to JTAG, but instead are converted to a different serial interface
through a chip level SCOM controller.
10.3 Debug Modes
The following sections describe the various debug modes supported by the A2 core. Each of these debug
modes supports a particular type of debug tool or debug task commonly used in embedded systems develop-
ment. For internal and external debug modes, the various debug event types are enabled by the setting of
corresponding fields in Debug Control Register 0 (DBCR0) or Debug Control Register 3 (DBCR3), and upon
their occurrence are recorded in the Debug Status Register (DBSR). The trace debug mode is controlled
through various SCOM accessible registers that enable the selection of debug and trigger signals that are
sent out on the external trace and trigger buses.
There are three debug modes:
• Internal debug mode
• External debug mode
• Trace debug mode
Version 1.3
October 23, 2012
User's Manual
A2 Processor
Debug Facilities
Page 399 of 864
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