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2.12.1 Privileged Instructions
An instruction that is hypervisor privileged must be in the hypervisor state (MSR[GS,PR] = 0b00) to success-
fully execute. If executed from guest privileged state (MSR[GS,PR] = 0b10), an embedded hypervisor privi-
lege exception occurs. A register that is hypervisor privileged must be in the hypervisor state (MSR[GS,PR] =
0b00) to be accessed. If accessed from guest privileged state (MSR[GS,PR] = 0b10), an embedded hyper-
visor privilege exception occurs.
All the instructions listed in Table 2-53 are privileged and cannot be executed in user mode; some instructions
are also hypervisor privileged and must be executed in hypervisor mode.
Table 2-53. Privileged Instructions
Hypervisor
Instruction
Privileged
dcbfep
dcbi
dcbstep
dcbtep
dcbtstep
dcbzep
dci
ehpriv
eratilx
Yes
erativax
Yes
eratre
Yes
eratsrx[.]
Yes
eratsx[.]
Yes
eratwe
Yes
icbiep
1. Applies to any SPR number with SPRN
2. Applies to SPR numbers listed as hypervisor privileged. See Table 14-1 Register Summary on page 530.
3. This instruction is hypervisor privileged when MSR[GS] = 1 and TLB0CFG[GTWE] = 0.
2.12.1.1 Cache Locking Instructions
The cache locking instructions (dcblc, dcbtls, dcbtstls, icblc, icbtls) are special and produce exceptions
according to the following expression:
if MSRP[UCLEP]=1 AND MSR[GS]=1
if MSR[PR]=1
Cache Locking Type Data Storage Interrupt
else
Embedded Hypervisor Privilege Interrupt
Version 1.3
October 23, 2012
Hypervisor
Instruction
Privileged
ici
icswepx[.]
lbepx
ldepx
lfdepx
lhepx
lwepx
mfmsr
1
2
mfspr
Yes
msgclr
Yes
msgsnd
Yes
mtmsr
1
2
mtspr
Yes
rfci
Yes
rfi
rfmci
Yes
= 1. See Privileged SPRs on page 122.
5
User's Manual
A2 Processor
Hypervisor
Instruction
Privileged
rfgi
stbepx
stdepx
stfdepx
sthepx
stwepx
tlbilx
EPCR[DGTMI] = 1
tlbivax
Yes
tlbre
Yes
tlbsrx.
EPCR[DGTMI] = 1
tlbsx
Yes
tlbsync
Yes
3
tlbwe
EPCR[DGTMI] = 1
3
tlbwec
EPCR[DGTMI] = 1
wrtee
wrteei
CPU Programming Model
Page 121 of 864
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