Dbcr0 - Debug Control Register 0 - IBM A2 User Manual

User's Manual
A2 Processor

14.5.16 DBCR0 - Debug Control Register 0

Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
32 EDM RO
33 IDM
34:35 RST
36 ICMP
37 BRT
38 IRPT
39 TRAP
40 IAC1
41 IAC2
42 IAC3
43 IAC4
Alphabetical Register Listing
Page 558 of 897
DBCR0
308
0x0000000000000000
N
Initial
Value
0b0 External Debug Mode
Reports the state of external debug mode.
0 External debug mode is disabled.
1 External debug mode is enabled. External debug mode is set, and the corre-
sponding debug action selected, from the decoded value of PCCR0[DBA] bits.
0b0 Internal Debug Mode
Enable internal debug mode. If MSR[DE] = 1, the occurrence of a debug event or the
recording of an earlier debug event in the Debug Status Register when MSR[DE] = 0 or
DBCR0[IDM] = 0 causes a debug interrupt.
0b00 Reset
00 No Action
01 Reset1
10 Reset2
11 Reset3
0b0 Instruction Completion Debug Event
0 ICMP debug events are disabled.
1 ICMP debug events are enabled when MSR[DE] = 1.
0b0 Branch Taken Debug Event
0 BRT debug events are disabled.
1 BRT debug events are enabled when MSR[DE] = 1.
0b0 Interrupt Taken Debug Event Enable
0 IRPT debug events are disabled.
1 IRPT debug events are enabled.
0b0 Trap Debug Event Enable
0 TRAP debug events cannot occur.
1 TRAP debug events can occur.
0b0 Instruction Address Compare 1 Debug Event Enable
0 IAC1 debug events cannot occur.
1 IAC1 debug events can occur.
0b0 Instruction Address Compare 2 Debug Event Enable
0 IAC2 debug events cannot occur.
1 IAC2 debug events can occur.
0b0 Instruction Address Compare 3 Debug Event Enable
0 IAC3 debug events cannot occur.
1 IAC3 debug events can occur.
0b0 Instruction Address Compare 4 Debug Event Enable
0 IAC4 debug events cannot occur.
1 IAC4 debug events can occur.
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
RO
Hypv
Hypv
Y
dcfg
Version 1.3
October 23, 2012