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4. Execute an rfi.
If the locking instruction is a clear lock instruction, to unlock the line, the handler should do the following:
1. Remove the line address from its list of locked lines.
2. Execute the appropriate clear lock instruction to unlock the cache line.
3. Modify SRR0 to point to the instruction immediately after the locking instruction that caused the DSI.
4. Execute an rfi.
Failure to update SRR0 to point to the instruction after the locking/unlocking instruction causes the exception
handler to be repeatedly invoked for the same instruction.
Effects of Other Cache Instructions on Locked Lines
The following cache instructions do not affect the state of a cache line's lock bit:
• dcbt (CT = 0)
• dcbtst (CT = 0)
If dcbt is performed to a line that is locked in the cache, dcbt takes no action. However, if the line is invalid
and therefore not locked, dcbt executes normally.
If a dcbtst (CT = 0) is performed to a line that is locked in the cache, dcbtst takes no action. If the line is
invalid and therefore not locked, dcbtst executes normally.
The following instructions invalidate and unlock a line in the data cache of the current processor. These
instructions are sent to the A2 system interface and can flush/invalidate and unlock caches on this processor
and caches in other processors in a multiprocessor system (See the system user's manual.)
• dcbf
• dcbi
• dcbz
• lwarx
• ldarx
• stwcx.
• stdcx.
Flash Clearing of Lock Bits:
The A2 core allows flash clear of the data cache lock bits under software control. The cache's lock bits can be
flash cleared through the CLFC control bit in XUCR.
Lock bits in both caches are cleared automatically upon power-up. A subsequent soft reset operation does
not clear the lock bits automatically. Software must use the CLFC controls if flash clearing of the lock bits is
desired after a soft reset. Setting the CLFC bit causes a flash clearing to be performed in a single CPU cycle,
after which the CLFC bit is automatically cleared (CLFC bits are not sticky).
Version 1.3
October 23, 2012
User's Manual
A2 Processor
Instruction and Data Caches
Page 181 of 864
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