Table 15-4. Fir0 Action1 Register (Fir0A1) - IBM A2 User Manual

Bits
44 fu_pc_err_regfile_parity, T0
45 fu_pc_err_regfile_parity, T1
46 fu_pc_err_regfile_parity, T2
47 fu_pc_err_regfile_parity, T3
48
49
50 scom_reg_parity_err
51 scom_reg_ack_err
52 xu_pc_err_wdt_reset, T0
53 xu_pc_err_wdt_reset, T1
54 xu_pc_err_wdt_reset, T2
55 xu_pc_err_wdt_reset, T3
56 xu_pc_err_llbust_attempt, T0
57 xu_pc_err_llbust_attempt, T1
58 xu_pc_err_llbust_attempt, T2
59 xu_pc_err_llbust_attempt, T3
60 xu_pc_err_llbust_failed, T0
61 xu_pc_err_llbust_failed, T1
62 xu_pc_err_llbust_failed, T2
63 xu_pc_err_llbust_failed, T3

Table 15-4. FIR0 Action1 Register (FIR0A1)

Register Short Name:
Register Address:
Initial Value:
Version 1.3
October 23, 2012
Initial
Function
Value
0
0
0
0
Reserved 0
Reserved 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FIR0A1
x'04' RW
0x00000000FFFFF0FF
An FU register file parity error was detected by thread 0. Hardware
error recovery will correct the data and update the array.
An FU register file parity error was detected by thread 1. Hardware
error recovery will correct the data and update the array.
An FU register file parity error was detected by thread 2. Hardware
error recovery will correct the data and update the array.
An FU register file parity error was detected by thread 3. Hardware
error recovery will correct the data and update the array.
Reserved
Reserved
A parity error was detected in any of the following SCOM-accessible
registers: PCCR0, ABDSR, IDSR, MPDSR, XDSR1, XDSR2, or
SPATTN. The specific register that caused the error can be deter-
mined by scanning out error reporting macro data from the PC unit
bcfg scan rings.
An invalid SCOM register access occurred either through an invalid
address or by an invalid read/write request to a valid address. This bit
can also be caused by an error in the SCOM satellite.
A watchdog timer reset was requested by thread 0.
A watchdog timer reset was requested by thread 1.
A watchdog timer reset was requested by thread 2.
A watchdog timer reset was requested by thread 3.
The XU livelock buster logic has detected a hang condition for thread
0. The thread priority will be increased.
The XU livelock buster logic has detected a hang condition for thread
1. The thread priority will be increased.
The XU livelock buster logic has detected a hang condition for thread
2. The thread priority will be increased.
The XU livelock buster logic has detected a hang condition for thread
3. The thread priority will be increased.
The XU livelock buster's attempt to fix a thread 0 hang was not suc-
cessful within the selected delay threshold period. Forward progress
on another hung thread will be attempted before returning to this one.
The XU livelock buster's attempt to fix a thread 1 hang was not suc-
cessful within the selected delay threshold period. Forward progress
on another hung thread will be attempted before returning to this one.
The XU livelock buster's attempt to fix a thread 2 hang was not suc-
cessful within the selected delay threshold period. Forward progress
on another hung thread will be attempted before returning to this one.
The XU livelock buster's attempt to fix a thread 3 hang was not suc-
cessful within the selected delay threshold period. Forward progress
on another hung thread will be attempted before returning to this one.
Access:
Scan Ring:
User's Manual
A2 Processor
Description
RW
bcfg
SCOM Accessible Registers
Page 709 of 864