User's Manual
A2 Processor
• Debug Facilities on page 399
• Performance Events and Event Selection on page 449
• Implementation Dependent Instructions on page 481
• Power Management Methods on page 525
• Register Summary on page 529
• SCOM Accessible Registers on page 701
This book contains the following appendixes:
• Processor Instruction Summary on page 737
• FU Instruction Summary on page 756
• Debug and Trigger Groups on page 761
• Instruction Execution Performance and Code Optimizations on page 833
• Programming Examples on page 861
Notation
The manual uses the following notational conventions:
• Active low signals are shown with an overbar (Active_Low).
• All numbers are decimal unless specified in some special way.
• 0bnnnn means a number expressed in binary format.
• 0xnnnn means a number expressed in hexadecimal format.
Underscores might be used between digits.
• RA refers to General Purpose Register (GPR) RA.
• (RA) refers to the contents of GPR RA.
• (RA|0) refers to the contents of GPR RA or to the value 0 if the RA field is 0.
• Bits in registers, instructions, and fields are specified as follows.
• Bits are numbered most-significant bit to least-significant bit, starting with bit 0.
• X
means bit p of register, instruction, or field X.
p
• X
means bits p through q of a register, instruction, or field X.
p:q
• X
means bits p, q,... of a register, instruction, or field X.
p,q,...
• X[p] means a named field p of register X.
• X[p:q] means named fields p through q of register X.
• X[p,q,...]
means named fields p, q,... of register X.
...
• ¬X means the ones complement of the contents of X.
• A period (.) as the last character of an instruction mnemonic means that the instruction records status
information in certain fields of the Condition Register as a side effect of execution, as described in
Section 12 Implementation Dependent Instructions on page 481.
About This Book
Page 32 of 864
Version 1.3
October 23, 2012