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eratilx instructions. By invalidating the ERAT arrays, a context-altering instruction forces the hardware to
refresh the ERAT entries with the updated information in the UTLB as each memory page is accessed (when
enabled by the appropriate MMUCR1[CSINV] setting).
Programming Note: Of the items in the preceding list of ERAT invalidating operations, the machine check
interrupt is not architecturally required to be context synchronizing, and thus is not guaranteed to cause inval-
idation of any ERAT arrays on implementations other than the A2 core. Consequently, software that is
intended to be portable to other implementations should not depend on this behavior and should insert the
appropriate architecturally-defined context synchronizing operation as necessary for desired operation.
6.7.2 ERAT Reset Behavior
During reset, the instruction and data ERATs are first flushed and then loaded with two initial entries that
perform the following functions:
• Map the reset code and data page and set I = 1, G = 1.
• Map the first 4 K page of effective address space ("page 0") that contains the initial exception vector
addresses and set ExtClass = 1.
The LRU watermark registers for both ERATs are also loaded with an initial value just below the two boot
entries. See Section 4.2 A2 Core State After Reset on page 154 for details regarding the boot entry contents,
and so forth
After reset, both of the ERAT LRU pointers are set to 0 (the first nonvalid entry). The LRU pointer (or simply
"LRU") is physically different from the LRU watermark register. The LRU value is subsequently incremented
toward the watermark value until there are no nonvalid slots left in the ERAT. At this point, and as long as all
slots at or below the watermark value in the ERAT are occupied by valid entries, normal pseudo-LRU
replacement policy takes effect for those entry numbers at or below the watermark.
6.7.3 Atomic Update of ERAT Entries
In previous embedded implementations, carefully planned software sequences and/or software locking was
required when updating TLB entries because of the partial updates to the entries that occur when writing two
or more parts of the entry. In the A2 design, each of the ERAT caches include four (1 per thread) 64-bit RPN
registers that are updated upon eratwe of the RPN portion (WS = 1). Both halves of the ERAT entry are then
updated atomically when eratwe is executed with WS = 0 (EPN portion). The value written into the RPN
portion of the entry is the data most recently written to the RPN holding register. This allows two or more
processing threads to update ERAT entries simultaneously (as long as the entry indexes are different, or
when the round-robin increment mode described below is enabled).
6.7.4 ERAT LRU Round-Robin Replacement Mode
Both of the ERAT entities contain a physical LRU mechanism for hardware replacement from the optional
MMU TLB. Two configuration mode bits (MMUCR1[IRRE] and MMUCR1[DRRE]) are used to change the
behavior of the I-ERAT and D-ERAT LRUs, the eratwe instruction, and the TLB reloads in the round-robin
replacement mode. In this mode, the LRU behaves as an atomically incrementing entry index for the eratwe
instruction, rather than using the RA register as the entry index. The ERAT LRU index number is incremented
(the mod number of entries below the watermark is described in Section 6.7.5) in a round-robin fashion each
time the effective (WS = 0) portion of the entry is written. In this way, multiple threads can update ERAT
entries in the same hardware structure without the need for software locking between threads for this shared
resource. Likewise, the LRU behaves as an atomically incrementing entry index for TLB reload events that
Version 1.3
October 23, 2012
User's Manual
A2 Processor
Memory Management
Page 205 of 864
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