Instruction And Data Caches; Data Cache Array Organization And Operation; Table 5-1. Data Cache Array Organization; Table 5-2. Cache Size And Parameters - IBM A2 User Manual

5. Instruction and Data Caches

The A2 core provides separate instruction and data cache controllers and arrays, which allow concurrent
access and minimize pipeline stalls. The storage capacity of the cache arrays is 16 KB each. Both cache
controllers have 64-byte lines. Both are set associative, with the data cache having 8-way set-associativity,
and the instruction cache having 4-way set associativity. The Power ISA instruction set provides a rich set of
cache management instructions for software-enforced coherency. The cache controllers interface to the
processor interface for connection to the system-on-a-chip environment.
Both the data and instruction caches support a 42-bit real address, and both are parity protected against soft
errors. The details of suggested interrupt handling are described in Instruction Cache Controller on page 170
and in Data Cache Controller on page 173
The rest of this chapter provides more detailed information about the operation of the instruction and data
cache controllers and arrays.

5.1 Data Cache Array Organization and Operation

The data cache is 8-way set-associative, with 32 sets and a 64-byte line size.
Table 5-1 illustrates generically the ways and sets of the cache arrays, while Table 5-2 provides specific
values for the parameters used in Table 5-1. As shown in Table 5-2, the tag field for each line in each way
holds the high-order address bits associated with the line that currently resides in that way. The middle-order
address bits form an index to select a specific set of the cache, while the six lowest-order address bits form a
byte-offset to choose a specific byte (or bytes, depending on the size of the operation) from the 64-byte cache
line.

Table 5-1. Data Cache Array Organization

Set 0
Set 1



n
Set – 2
n
Set – 1

Table 5-2. Cache Size and Parameters

w
Array Size
16 KB
Version 1.3
October 23, 2012
Way 0 Way 1
Line 0 Line
Line 1 Line



n
Line – 2 Line 2
n
Line – 1 Line 2
n
(Ways) (Sets)
8 32

Way

n
Line (

n
+ 1 Line (
 
 
 

n
– 2 Line (

n
– 1 Line (
Tag
Address Bits
A
22:52
User's Manual
A2 Processor
w w
– 2 Way
w n w
– 2) Line (
w n w
– 2) + 1 Line ( – 1)
 
 
 
w n wn
– 1) – 2 Line
w n wn
– 1) – 1 Line
Set Byte Offset
Address Bits Address Bits
A A
53:57 58:63
Instruction and Data Caches
Page 169 of 864
– 1
n
– 1)
n
+ 1
– 2
– 1