Memory Management Unit Control Register (Mmucr); Figure 5-3. Memory Management Unit Control Register (Mmucr) - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core

5.7.1 Memory Management Unit Control Register (MMUCR)

The MMUCR is written from a GPR using
MMUCR[STID] is updated with the TID field of the selected TLB entry when a tlbre instruction is executed.
Conversely, the TID field of the selected TLB entry is updated with the value of the MMUCR[STID] field when
a tlbwe instruction is executed. Other functions associated with the STID and other fields of the MMUCR are
described in more detail in the sections that follow.
The following figure illustrates the MMUCR.
SWOA
0 6 7 8 9 10 11 12 13 14 15 16

Figure 5-3. Memory Management Unit Control Register (MMUCR)

0:6
7 SWOA
8
9 U1TE
10 U2SWOAE
11
12 DULXE
13 IULXE
14
15 STS
16:23
24:31 STID
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mtspr , and can be read into a GPR using mfspr . In addition, the
U2SWOAE IULXE
DULXE STS
U1TE
Reserved
Store Without Allocate
0 Cacheable store misses allocate a line in the
data cache.
1 Cacheable store misses do not allocate a line
in the data cache.
Reserved
U1 Transient Enable
0 Disable U1 storage attribute as transient
storage attribute.
1 Enable U1 storage attribute as transient
storage attribute.
U2 Store without Allocate Enable
0 Disable U2 storage attribute control of store
without allocate.
1 Enable U2 storage attribute control of store
without allocate.
Reserved
Data Cache Unlock Exception Enable
0 Data cache unlock exception is disabled.
1 Data cache unlock exception is enabled.
Instruction Cache Unlock Exception Enable
0 Instruction cache unlock exception is disabled.
1 Instruction cache unlock exception is enabled.
Reserved
Search Translation Space
Reserved
Search Translation ID
STID
23 24
If MMUCR[U2SWOAE] = 1, this field is ignored.
If MMUCR[U2SWOAE] = 1, the U2 storage
attribute overrides MMUCR[SWOA].
dcbf in user mode will cause Cache Locking
exception type Data Storage interrupt when
MMUCR[DULXE] is 1.
icbi in user mode will cause Cache Locking
exception type Data Storage interrupt when
MMUCR[IULXE] is 1.
Specifies the value of the translation space (TS)
tlbsx[.]
field for the instruction
Specifies the value of the process identifier to be
compared against the TLB entry's TID field for
tlbsx[.]
the instruction; also used to transfer a
tlbre
TLB entry's TID value for the
instructions.
Preliminary
31
tlbwe
and
mmu.fm.
September 12, 2002