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Bits
Field Name
50:51
IAC3ER
52:53
IAC4US
54:55
IAC4ER
56
///
57
IAC34M
58:63
///
10.7.3 Debug Control Register 2 (DBCR2)
DBCR2 is an SPR that is used to configure DAC and DVC debug events. DBCR2 can be written from a GPR
using mtspr and can be read into a GPR using mfspr.
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits
Field Name
32:33
DAC1US
Version 1.3
October 23, 2012
Initial
Value
0b00
Instruction Address Compare 3 Effective/Real Mode
00
Effective: IAC3 debug events are based on effective addresses.
01
Not Implemented.
10
Effective IS0: IAC3 debug events are based on effective addresses and if
MSR[IS] = 0.
11
Effective IS1: IAC3 debug events are based on effective addresses and if
MSR[IS] = 1.
0b00
Instruction Address Compare 4 User/Supervisor Mode
00
Enabled: IAC4 debug events can occur.
01
Reserved.
10
Enabled PR0: IAC4 debug events can occur only if MSR[PR] = 0.
11
Enabled PR1: IAC4 debug events can occur only if MSR[PR] = 1.
0b00
Instruction Address Compare 4 Effective/Real Mode
00
Effective: IAC4 debug events are based on effective addresses.
01
Not implemented.
10
Effective IS0: IAC4 debug events are based on effective addresses and if
MSR[IS] = 0.
11
Effective IS1: IAC4 debug events are based on effective addresses and if
MSR[IS] = 1.
0b0
Reserved
0b0
Instruction Address Compare 3/4 Mode
0
Exact address compare.
1
Address bit match.
0x0
Reserved
DBCR2
310
0x0000000000000000
N
Initial
Value
0b00
Data Address Compare 1 User/Supervisor Mode
00
Enabled: DAC1 debug events can occur.
01
Reserved.
10
Enabled PR0: DAC1 debug events can occur only if MSR[PR] = 0.
11
Enabled PR1: DAC1 debug events can occur only if MSR[PR] = 1.
Description
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
User's Manual
A2 Processor
Hypv
Hypv
Y
AM
func
Debug Facilities
Page 419 of 864
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