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lar page table. To accomplish this, the operating system needs to install 16 MB/64 KB = 256 duplicates of the
16 MB size PTE so that the first virtual address falling in this 1/16 "chunk" of the 256 MB indirect page will
fetch and install one of the 16 MB PTE duplicates. Subsequently, any virtual address falling in this 16 MB
range is translated by the installed direct 16 MB entry. Installing PTEs in a page table with page sizes smaller
than the associated indirect entry's sub-page size is considered a programming error and should be avoided
(that is, it results in certain "holes" in virtual memory that cannot be translated via the hardware page table).
6.16.3 Hardware Page Table Entry Format
The format of the 64-bit hardware PTE is shown in Figure 6-6. The PTE contains a logical page number (or,
under certain circumstances, a real page number) and other page-related attribute and protection informa-
tion. When valid, the PTE is combined with the virtual address tag information from the original transaction
that requested this page table entry fetch before being passed through the LRAT facility and finally being
stored in the TLB cache.
Figure 6-6. Page Table Entry Format
0
ARPN(12:51)
ARPN Field
WIMGE Field
R and C Fields
U0:U3 Field
SW0 and SW1 Fields
PS Field
Version 1.3
October 23, 2012
39 40
44 45 46 49 50 51 52
R U0:U3
WIMGE
The abbreviated real page number. Because this processor supports a 42-bit real
address range, ARPN[12:21], or bits 0 to 9 of the PTE, are assumed to be zero and
are ignored. ARPN[22:51] are used in the determination of the logical address for
this implementation. Bit 51 is the LSb for the ARPN because PTEs must specify a
page size of 4 K or larger per the architecture.
Storage control attributes associated with this page.
Reference and Change bits. The R and C bits in a given PTE are not updated by
hardware in any way. See Section 6.16.5 Hardware Page Table Errors and Excep-
tions to see how the base access permission bits are modified by the R and C bits to
form the storage access control bits that are actually stored into the TLB entry.
User definable storage control bits.
Available for software defined use.
Page Size for this entry. This 4-bit field is prepended with 0b0 to form a 5-bit, power
of 2 1 K page size encoding (0b0 || PS), and PS must specify a page size of 4 K or
larger. This processor supports only a subset of power of 4 1 K page sizes. There-
fore, bit 55 of the PTE (the LSb of the power of 2 1 K page size) is treated as zero
always and ignored. Supported values of the PS field for this implementation include:
0b0010 (4 KB for sub-page size of 4 KB only), 0b0110 (64 KB), 0b1010 (1 MB), and
0b1110 (16 MB).
55 56
C
PS
BAP[0:5]
User's Manual
A2 Processor
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V
Memory Management
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