IBM A2 User Manual page 857

Table D-4. Interrupt Conditions
Interrupt
Decrementer Decrementer
FIT Fixed interval timer tick
WDOG Watchdog timeout
DTLB D-ERAT miss and CCR2[NOTLB] = 1
Data TLB miss and CCR2[NOTLB] = 0
ITLB I-ERAT miss and CCR2[NOTLB] = 1
Instruction TLB miss and CCR2[NOTLB] = 0
Debug Instruction complete
Trap instruction
Instruction address compare
Data address compare
Branch taken
rfi instruction
Interrupt taken
Instruction value compare
Unconditional debug event
Imprecise event
Vector Unavailable Vector type instruction executed with MSR[SPV] = 0
Doorbell DBELL message received
Doorbell Critical DBELL_CRIT message received
Guest Doorbell G_DBELL message received
Guest Doorbell G_DBELL_CRIT message received
Critical
Guest Doorbell G_DBELL_MC message received
Machine Check
Hypv Priv Hypervisor privilege Instruction when (MSR[PR] = 0 and
MSR[GS] = 1)
Hypervisor privilege SPR when (MSR[PR] = 0 and MSR[GS] = 1)
TLB management instruction executed with invalid MAS configu-
ration
ehpriv executed
Instr LRAT Instruction page table entry reload missed in the LRAT
Data LRAT Data page table entry reload missed in the LRAT
1. N indicates that the instruction causing the condition is flushed. NP1 indicates that the instruction following the one causing the
condition is flushed.
2. AXU implementation dependent.
3. Precise mode can be achieved by enabling single instruction mode.
4. Data value compare events for loads are imprecise.
Version 1.3
October 23, 2012
(Sheet 4 of 5)
Condition
Stage
Precision
Flushed
Async EX4
Async EX4
Async EX4
Precise EX4
Precise EX4
Precise
Precise EX4
Precise
Precise
4
Precise
Precise
Precise
Async
Precise
Async
Imprecise
Precise EX4
Async EX4
Async EX4
Async EX4
Async EX4
Async EX4
Precise EX4
Precise EX4
Precise EX4
Instruction Execution Performance and Code Optimizations
User's Manual
A2 Processor
1
Type NIA
NP1 0x160
NP1 0x180
N 0x1A0
N 0x1C0
N 0x1E0
NP1 0x0F0
N
N 0x200
NP1 0x2C0
N 0x2A0
NP1 0x2C0
N 0x2E0
N 0x2E0
N 0x320
N 0x340
N 0x340
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