Table of Contents
Advertisement
User's Manual
A2 Processor
6.17.27 Logical Page Exception Register Upper (LPERU) ........................................................... 274
6.17.28 MAS Register Update Summary ...................................................................................... 275
6.18 Storage Control Registers (Non-Architected) .............................................................................. 277
6.18.1 Memory Management Unit Control Register 0 (MMUCR0) ............................................... 277
6.18.2 Memory Management Unit Control Register 1 (MMUCR1) ............................................... 280
6.18.3 Memory Management Unit Control Register 2 (MMUCR2) ............................................... 287
6.18.4 Memory Management Unit Control Register 3 (MMUCR3) ............................................... 290
7. CPU Interrupts and Exceptions .............................................................................. 293
7.1 Overview ....................................................................................................................................... 293
7.2 Directed Interrupts ......................................................................................................................... 293
7.3 Interrupt Classes ........................................................................................................................... 294
7.3.1 Asynchronous Interrupts ...................................................................................................... 294
7.3.2 Synchronous Interrupts ........................................................................................................ 294
7.3.2.1 Synchronous, Precise Interrupts .................................................................................. 294
7.3.2.2 Synchronous, Imprecise Interrupts ............................................................................... 295
7.3.3 Critical and Noncritical Interrupts ......................................................................................... 296
7.3.4 Machine Check Interrupts .................................................................................................... 296
7.4 Interrupt Processing ...................................................................................................................... 297
7.4.1 Partially Executed Instructions ............................................................................................. 299
7.5 Interrupt Processing Registers ...................................................................................................... 300
7.5.1 Register Mapping ................................................................................................................. 301
7.5.2 Machine State Register (MSR) ............................................................................................ 301
7.5.3 Machine State Register Protect (MSRP) ............................................................................. 303
7.5.4 Embedded Processor Control Register (EPCR) .................................................................. 304
7.5.5 Save/Restore Register 0 (SRR0) ......................................................................................... 305
7.5.6 Save/Restore Register 1 (SRR1) ......................................................................................... 306
7.5.7 Guest Save/Restore Register 0 (GSRR0) ........................................................................... 308
7.5.8 Guest Save/Restore Register 1 (GSRR1) ........................................................................... 308
7.5.9 Critical Save/Restore Register 0 (CSRR0) .......................................................................... 310
7.5.10 Critical Save/Restore Register 1 (CSRR1) ........................................................................ 311
7.5.11 Machine Check Save/Restore Register 0 (MCSRR0) ....................................................... 313
7.5.12 Machine Check Save/Restore Register 1 (MCSRR1) ....................................................... 313
7.5.13 Data Exception Address Register (DEAR) ......................................................................... 315
7.5.14 Guest Data Exception Address Register (GDEAR) ........................................................... 316
7.5.15 Interrupt Vector Prefix Register (IVPR) .............................................................................. 318
7.5.16 Guest Interrupt Vector Prefix Register (GIVPR) ................................................................ 318
7.5.17 Exception Syndrome Register (ESR) ................................................................................. 318
7.5.18 Guest Exception Syndrome Register (GESR) ................................................................... 320
7.5.19 Machine Check Status Register (MCSR) ........................................................................... 322
7.6 Interrupt Definitions ....................................................................................................................... 323
7.6.1 Critical Input Interrupt ........................................................................................................... 326
7.6.2 Machine Check Interrupt ...................................................................................................... 327
7.6.2.1 Machine Check Status Register (MCSR) ..................................................................... 329
7.6.3 Data Storage Interrupt ......................................................................................................... 330
7.6.4 Instruction Storage Interrupt ................................................................................................ 334
7.6.5 External Input Interrupt ........................................................................................................ 336
7.6.6 Alignment Interrupt ............................................................................................................... 337
7.6.7 Program Interrupt ................................................................................................................. 338
Contents
Page 10 of 864
Version 1.3
October 23, 2012
Advertisement
Table of Contents
