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User's Manual
A2 Processor
12.5.4 Coprocessor-Request Block
A coprocessor-request block (CRB) must be located on a 128-byte boundary; otherwise, the icswx instruc-
tion specifying such an unaligned CRB recognizes an alignment interrupt.
A CRB is, at most, 64 bytes long. The definition of the contents of a CRB depends upon the coprocessor type
and coprocessor directive that is specified by the icswx instruction. See the coprocessor architecture for
details.
If the implementation forms a CCW, storing it into bytes 0:3 of the CRB, execution of an icswx instruction is
subject to a storage-protection data storage interrupt.
A CRB is not subject to exceptions related to storage-access WIMG bits.
Figure 12-3. Generic Coprocessor-Request Block
Byte
0
Implementation-Dependent CCW
4
63
0
Byte
Meaning
0:3
Implementation-dependent CCW.
4:63
Bytes 0:63, the data field, are defined by each coprocessor type.
Programming Note: When little endian is in effect for the storage containing a CRB, byte-reversal stores
must be performed in setting up a CRB data field such that the big-endian definition in the CRB contents is
maintained. This includes setup by the program of any byte-reversed integer value whose length is a power
of 2 and is normally subject to reversal.
12.5.4.1 Available Coprocessor Register (ACOP)
The ACOP is a 64-bit register. Available Coprocessor Register bits are numbered 0 (most-significant) to 63
(least-significant). The Available Coprocessor Register provides a 64-bit mask where a bit position corre-
sponds to a coprocessor type. When a bit position is one, at least one coprocessor of that coprocessor type
might be available. When a bit position is zero, no coprocessor of that coprocessor type is available.
The Available Coprocessor Register can be read using mfspr and can be written using mtspr. Only the least-
significant 32 bits of the Available Coprocessor Register are implemented. The most-significant 32 bits of the
Available-Coprocessor Register are treated as reserved. Each thread has an ACOP register.
When icswx is issued by a program in hypervisor or privileged state, ACOP checking does not apply. When
icswx is issued by a program in problem state, ACOP checking applies. When ACOP checking applies and
fails, an unavailable coprocessor type (UCT) exception is recognized and a DSI occurs.
Implementation Dependent Instructions
Page 520 of 864
Data Field
31
Version 1.3
October 23, 2012
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