Lsu Performance Events Table; Table 11-6. Lsu Performance Events Table - IBM A2 User Manual

User's Manual
A2 Processor

11.4.4 LSU Performance Events Table

Table 11-6. LSU Performance Events Table

(Use XESR3 and XESR4 for corresponding multiplexer selects)
Note: See the unit performance events table column descriptions in Section 11.3.3 on page 457.
Event Name
(Tag: B/C/E/S/V)
Committed Stores (V)
Committed Store Misses (V) Number of completed store commands that missed the L1 data
Committed Load Misses (V)
Committed Cache-
Inhibited Load Misses (V)
Committed Cacheable Loads
(V)
Committed DCBT Misses (V) Number of completed dcbt[st][ls][ep] commands that missed
Committed DCBT Hits (V)
Performance Events and Event Selection
Page 462 of 864
(Sheet 1 of 3)
Description
Number of completed store commands.
• Microcoded instructions count more than once.
• Does not count syncs, TLB operations, dcbz, icswx, or
data cache management instructions.
• Includes stcx, but does not wait for stcx complete
response from the L2.
• Includes cache-inhibited stores.
cache.
• Microcoded instructions can be counted more than once.
• Does not count syncs, TLB operations, dcbz, icswx, or
data cache management instructions.
• Includes stcx, but does not wait for stcx complete
response from the L2.
• Does not includes cache-inhibited stores.
Number of completed load commands that missed the L1 data
cache.
• Microcoded instructions can be counted more than once.
• Does not count dcbt[st][ls][ep].
• Includes larx.
• Does not includes cache-inhibited loads.
Number of completed cache-inhibited load commands.
• Microcoded instructions can be counted more than once.
• Does not count dcbt[st][ls][ep].
• Does not include cacheable loads.
Number of completed cacheable load commands.
• Microcoded instructions can be counted more than once.
• Does not count dcbt[st][ls][ep].
• Includes larx.
• Does not includes cache-inhibited loads.
the L1 data cache.
• Does not include touch operations that were dropped due
to the following:
1. Unsupported TH(CT) fields.
2. Translated to cache-inhibited.
3. Exception detected on dcbt[st][ep].
Number of completed dcbt[st][ls][ep] commands that hit the
L1 data cache.
• Does not include touch operations that were dropped due
to the following:
1. Unsupported TH(CT) fields.
2. Translated to cache-inhibited.
3. Exception detected on dcbt[st][ep].
Per Input_Sel Mux_Sel
Core Options Decode
Event? (Tx_Events) (Mux 0:31)
No any
No any
No any
No any
No any
No any
No any
Version 1.3
October 23, 2012
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