Figure 6-2. Effective-To-Real Address Translation Flow; Table 6-2. Page Size And Real Address Formation - IBM A2 User Manual

User's Manual
A2 Processor

Figure 6-2. Effective-to-Real Address Translation Flow

MSR[GS]
LPID
7
0
Virtual Page Number
Compare Virtual Page Number
Matching Entry RPN

Table 6-2. Page Size and Real Address Formation

1
SIZE
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
1. The Power ISA page sizes are defined as a power of 2  1 KB sizes and represented by a 5-bit value. The page sizes supported by
A2 all happen to be power of 4  1 KB sizes. For this reason, the LSB of the architected page size encoding is assumed to be zero
always and is not implemented in A2.
Memory Management
Page 192 of 864
MSR[DS] for data storage accesses
MSR[IS] for instruction fetch
PID
0 13 0
88-bit Virtual Address
22
Page Access Control
and Attributes
Page Size
not supported
4 KB
not supported
64 KB
not supported
1 MB
not supported
16 MB
not supported
not supported
1 GB
not supported
not supported
not supported
not supported
not supported
64-bit Effective Address
Effective Page Number (EPN)
512-entry TLB
RPN0:n-1
Real Page Number (RPN)
42-Bit Real Address
Note: n = 64–log
RPN Bits Required to be 0
not supported
None
not supported
RPN = 0
48:51
not supported
RPN = 0
44:51
not supported
RPN = 0
40:51
not supported
not supported
RPN = 0
34:51
not supported
not supported
not supported
not supported
not supported
Offset
n–1 n 63
Offset
n–1 n 63
page size
( )
2
Real Address
not supported
RPN || EA
22:51 52:63
not supported
RPN || EA
22:47 48:63
not supported
RPN || EA
22:43 44:63
not supported
RPN || EA
22:39 40:63
not supported
not supported
RPN || EA
22:33 34:63
not supported
not supported
not supported
not supported
not supported
Version 1.3
October 23, 2012