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User's Manual
A2 Processor
Table 10-9. Ram Data Register Low (RAMDL)
Register Short Name:
Register Address:
Initial Value:
Bits
Function
0:31
Reserved
32:63
Ram Data
(32 to 63)
10.8.3 Example Ram Mode Procedures
10.8.3.1 SPR Read/Write Using GPR as Temporary Storage
This section shows the process for stopping a thread, enabling Ram operations, and performing an SPR
access through Rammed instructions. This example reads the MSR, modifies its value, and stores it back;
using a GPR as temporary storage. Specific values for the thread, GPR, and SPR are shown in this example
for clarity, but can be extended to other facilities.
Assumptions and common actions:
• After Ram mode started, these settings remain constant: RAMC
'01' (selects thread 1).
• Assumes that the 64-bit RAMIC register is used to set Ram instruction and controls simultaneously. The
procedure describes PowerPC instructions written to the RAMIC register. Assume that RAMC
'1', RAMC
Thread Select
• GPR r1 is used as a temporary register (needs to be saved off and restored).
• Assumes that the RAMD register is read to retrieve all 64 bits of Ram data in one operation.
• "Verify Ram status" means [SCOM read RAMC; verify bits 61:62 = '00' and bit 63 = '1']
Read; modify; write the MSR:
1. Stop execution on the selected thread and enable Ram operations.
• Stop thread 1 [SCOM write THRCTL(33) = '1'].
• Verify thread 1 stopped [SCOM read THRCTL(41) = '0'].
• Enable Ram operations [SCOM write PCCR0 = 0x0000_0000_4000_0000].
2. Save off original data from temporary register (r1).
• Result of Rammed instruction loads r1 into RAMD [SCOM write RAMIC Instr = "xori r1, r1, 0"].
• Verify Ram status.
• Save off RAMD [SCOM read RAMD] to SaveReg.
3. Read MSR and set desired bits.
• Copy MSR to r1 [SCOM write RAMIC Instr = "mfspr r1, MSR"]; Verify Ram status.
• Get MSR from RAMD [SCOM read RAMD].
• Modify MSR bits to new value.
Debug Facilities
Page 434 of 864
RAMDL
x'2F' RW
0x0000000000000000
Initial
Value
0
0
When in Ram mode, the results of any instruction operation are written to the Ram Data Reg-
isters.
The Ram Data Registers are updated upon activation of RAMC
= '01', and RAMC
Execute
Access:
Scan Ring:
Description
Ram Mode
= '1' is written along with the instruction.
RW
func
.
Done
= '1' and RAMC
Thread Select
Ram Mode
Version 1.3
October 23, 2012
=
=
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