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User's Manual
A2 Processor
6.5.1 Write-Through (W)
The A2 core data cache ignores the write-through attribute. The data for all store operations is written to
memory, as opposed to only being written into the data cache. If the referenced line also exists in the data
cache (that is, the store operation is a "hit"), the data is also written into the data cache. An alignment excep-
tion occurs if a dcbz instruction targets a memory page that is either write-through required or caching inhib-
ited. A data storage exception occurs if an lwarx, ldarx, stwcx., or stdcx. instruction targets a memory page
that is either write-through required or caching inhibited.
See Instruction and Data Caches on page 169 for more information about the handling of accesses to write-
through storage.
6.5.2 Caching Inhibited (I)
If a memory page is marked as caching inhibited (I = 1), all load, store, and instruction fetch operations
perform their access in memory, as opposed to in the respective cache. If I = 0, the page is cacheable; and
the operations can be performed in the cache. An alignment exception occurs if a dcbz instruction targets a
memory page that is either write-through required or caching inhibited. A data storage exception occurs if an
lwarx, ldarx, stwcx., or stdcx. instruction targets a memory page that is either write-through required or
caching inhibited.
It is a programming error for the target location of a load, store, dcbz, or fetch access to caching inhibited
storage to be in the respective cache; the results of such an access are undefined. It is not a programming
error for the target locations of the other cache management instructions to be in the cache when the caching
inhibited storage attribute is set. The behavior of these instructions is defined for both I = 0 and I = 1 storage.
See Instruction and Data Caches on page 169 for more information about the handling of accesses to
caching inhibited storage.
6.5.3 Memory Coherence Required (M)
The memory coherence required (M) storage attribute is defined by the architecture to support cache and
memory coherency within multiprocessor shared memory systems. If a TLB entry is created with M = 1, any
storage accesses to the page associated with that TLB entry are indicated, using the corresponding transfer
attribute interface signal, as being memory coherence required. However, the setting has no effect on the
operation within the A2 core.
6.5.4 Guarded (G)
The guarded storage attribute is provided to control "speculative" access to "non-well-behaved" memory loca-
tions. Storage is said to be "well-behaved" if the corresponding real storage exists and is not defective, and if
the effects of a single access to it are indistinguishable from the effects of multiple identical accesses to it. As
such, data and instructions can be fetched out-of-order from well-behaved storage without causing undesired
side effects.
In general, storage that is not well-behaved should be marked as guarded. Because such storage might
represent a control register on an I/O device or might include locations that do not exist, an out-of-order
access to such storage might cause an I/O device to perform unintended operations or might result in a
machine check exception. For example, if the input buffer of a serial I/O device is memory-mapped, an out-of-
order or speculative access to that location might result in the loss of an item of data from the input buffer, if
the instruction execution is interrupted and later re-attempted.
Memory Management
Version 1.3
Page 196 of 864
October 23, 2012
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