Instruction Cache Throttling Control Register (Ictc) - IBM PowerPC 750GX User Manual

2.1.3 Instruction Cache Throttling Control Register (ICTC)

Reducing the rate of instruction fetching can control junction temperature without the complexity and over-
head of dynamic clock control. System software can control instruction forwarding by writing a nonzero value
to the supervisor-level ICTC register. The overall junction temperature reduction comes from the dynamic
power management of each functional unit when the 750GX is idle in between instruction fetches. PLL
(phase-locked loop) and DLL (delay-locked loop) configurations are unchanged.
Instruction-cache throttling is enabled by setting ICTC[E] and writing the instruction forwarding interval into
ICTC[FI]. Enabling, disabling, and changing the instruction forwarding interval immediately affect instruction
forwarding.
The ICTC register can be accessed with the mtspr and mfspr instructions using SPR 1019.
0 1 2 3 4 5 6
Bits Field Name
0:22 Reserved
23:30
31
gx_02.fm.(1.2)
March 27, 2006
Reserved
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved for future use. The system software should always write zeros to these bits
when writing to the THRM SPRs.
Instruction forwarding interval expressed in processor clocks.
0x00 0 clock cycles
0x01 1 clock cycle
FI
.
.
0xFF 255 clock cycles
Cache throttling enable
E 0 Disable instruction-cache throttling.
1 Enable instruction-cache throttling.
IBM PowerPC 750GX and 750GL RISC Microprocessor
Description
User's Manual
FI E
Programming Model
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