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User's Manual
A2 Processor
Table 3-1. Data Operand Definitions
Storage Access Instruction Type
Word
Doubleword
Note: An "x" in an address bit position indicates that the bit can be 0 or 1 regardless of the state of other bits in the address.
The alignment of the operand effective address of some storage access instructions can affect performance
and in some cases can cause an alignment exception to occur. For such storage access instructions, the best
performance is obtained when the storage operands are naturally aligned. Table 2-11 on page 90 summa-
rizes the effects of alignment on those storage access instruction types for which such effects exist.
3.1.2 Effective Address Calculation
For a storage access instruction, if the sum of the effective address and the operand length exceeds the
maximum effective address of 2
itself crosses the maximum address boundary), the result of the operation is undefined, as specified by the
architecture. The A2 core performs the operation as if the storage operand wrapped around from the
maximum effective address to effective address 0. Software, however, should not depend upon this behavior,
so that can be ported to other implementations that do not handle such accesses in the same manner. Soft-
ware should ensure that no data storage operands cross the maximum address boundary.
Note: Because instructions are words and because the effective addresses of instructions are always implic-
itly on word boundaries, an instruction storage operand cannot cross any word boundary, including the maxi-
mum address boundary.
Effective address arithmetic, which calculates the starting address for storage operands, wraps around from
the maximum address to address 0, for all effective address computations except next sequential instruction
fetching.
3.1.3 Data Storage Addressing Modes
The A2 core supports the following data storage addressing modes.
• Base + displacement (D-mode) addressing mode:
The 16-bit D field is sign-extended to 64 bits and added to the contents of the GPR designated by RA, or
to zero if RA = 0. The 64-bit sum forms the effective address of the data storage operand.
Note: In 32-bit mode, the A2 core forces bits 0:31 of the calculated 64-bit effective address to zeros.
• Base + index (X-mode) addressing mode:
The contents of the GPR designated by RB (or the value 0 for lswi and stswi) are added to the contents
of the GPR designated by RA, or to zero if RA = 0;
FU Programming Model
Page 128 of 864
64
– 1 for 64-bit mode or 2
Operand Length
4 bytes
8 bytes
32
-1 in 32-bit mode (that is, the storage operand
A[60:63] if aligned
0bxx00
0bx000
Version 1.3
October 23, 2012
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