Mas8_Mas1 Register - IBM A2 User Manual

6.17.18 MAS8_MAS1 Register

The MAS8_MAS1 register is written from a 64-bit GPR using mtspr and can be read into a 64-bit GPR using
mfspr. This register is replicated for all processing threads. MAS8_MAS1 is used as a 64-bit register alias for
the MAS8 and MAS1 registers combined. It allows software to configure or read both the MAS8 and MAS1
with one 64-bit move to or from operation. The MAS8 and MAS1 field formats of this register are identical to
those of the 32-bit versions of these registers (entry contents).
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
0:31 MAS8
32:63 MAS1
Version 1.3
October 23, 2012
MAS8_MAS1
349
0x0000000000000000
Y
Initial
Value
0x0 MMU Assist Register 8
This field is an alias of MAS8[32:63].
0x0 MMU Assist Register 1
This field is an alias of MAS1[32:63].
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
User's Manual
A2 Processor
Hypv
Hypv
Y
HM
func
Memory Management
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