Fixed Interval Timer (Fit); Table 9-6. Fixed Interval Timer Period Selection - IBM A2 User Manual

User's Manual
A2 Processor
Bits Field Name Initial Value
32:63 UDEC 0x7FFFFFFF User Decrementer
Using mtspr to force the UDEC to 0 does not cause a user decrementer exception, and thus does not cause
TSR[UDIS] to be set. However, if a time base clock causes a decrement from a UDEC value of 1 to occur
simultaneously with the writing of the UDEC by an mtspr instruction, then the decrementer exception does
occur, TSR[UDIS] is set, and the UDEC is written with the value from the mtspr.
For software to quiesce the activity of the UDEC and eliminate all UDEC exceptions, follow this procedure:
1. Write 0 to TCR[UDIE]. This prevents a user decrementer exception from causing a user decrementer
interrupt.
2. Write 0 to the UDEC to halt decrementing. Although this action does not itself cause a user decrementer
exception, it is possible that a decrement from a UDEC value of 1 has occurred since the last time that
TSR[UDIS] was cleared.
3. Write 1 to TSR[UDIS] (UDEC Interrupt Status bit). This clears the user decrementer exception by setting
TSR[UDIS] to 0. Because the UDEC is no longer decrementing (due to having been written with 0 in step
2), no further User Decrementer exceptions are possible.

9.4 Fixed Interval Timer (FIT)

The FIT provides a mechanism for causing periodic exceptions with a regular period. The FIT is typically used
by system software to invoke a periodic system maintenance function, executed by the fixed interval timer
interrupt handler.
A fixed interval timer exception occurs on a 01 transition of a selected bit from the time base. Note that a
fixed interval timer exception also occurs if the selected time base bit transitions from 01 due to an mtspr
instruction that writes 1 to that time base bit when its previous value was 0.
The Fixed Interval Timer Period (FP) field of the TCR selects one of 4 bits from the time base, as shown in
Table 9-6.

Table 9-6. Fixed Interval Timer Period Selection

TCR[FP] Time Base Bit
0b00
0b01
0b10
0b11
Timer Facilities
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The User Decrementer (UDEC) is a 32-bit decrementing counter that provides a mechanism
for causing a user decrementer interrupt after a programmable delay. The contents of the User
Decrementer are treated as a signed integer.
Note: If TCR[UD] = 0, this access to this register is treated as an illegal SPR.
Period
(Time Base Clocks)
11
TBL 2 clocks
21
15
TBL 2 clocks
17
19
TBL 2 clocks
13
23
TBL 2 clocks
9
Description
Period Period
(32 MHz Clock) (1.6 GHz Clock)
64.00 s 1.28 s
20.48 s
1.02 ms
327.68 s
16.38 ms
262.14 ms 5.24 ms
Period
(2.3 GHz Clock)
.89 s
14.25 s
227.95 s
3.65 ms
Version 1.3
October 23, 2012