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User's Manual
A2 Processor
Bits
Field Name
51
ME
52
FE0
53
///
54
DE
55
FE1
56:57
///
58
IS
59
DS
60:63
///
Alphabetical Register Listing
Page 552 of 897
Initial
Value
0b0
Machine Check Enable
0
Machine check interrupts are disabled.
1
Machine check interrupts are enabled.
0b0
Floating-Point Exception Mode 0
Sets floating-point exception mode.
0b0
Reserved
0b0
Debug Interrupt Enable
0
Debug interrupts are disabled.
1
Debug interrupts are enabled if DBCR0[IDM] = 1.
0b0
Floating-Point Exception Mode 1
Sets floating-point exception mode.
0b00
Reserved
0b0
Instruction Address Space
0
The processor directs all instruction fetches to address space 0 (TS = 0 in the rel-
evant TLB entry).
1
The processor directs all instruction fetches to address space 1 (TS = 1 in the rel-
evant TLB entry).
0b0
Data Address Space
0
The processor directs all data storage accesses to address space 0 (TS = 0 in the
relevant TLB entry).
1
The processor directs all data storage accesses to address space 1 (TS = 1 in the
relevant TLB entry).
0b0000 Reserved
Description
Version 1.3
October 23, 2012
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