Fault Isolation Register 0 And Associated Registers - IBM A2 User Manual

Bits
32:35 Error Injection Thread Select
36:39
40 I-Cache Parity Error
41 I-Cache Directory Parity Error
42 D-Cache Parity Error
43 D-Cache Directory Parity Error
44 XU Register File Parity Error
45 FU Register File Parity Error
46 SPRG Array ECC Error
47 Inbox Array ECC Error
48 Outbox Array ECC Error
49 Livelock Buster Attempted
50 Livelock Buster Failed
51 Watchdog Timer Reset
52 SCOM Register Parity Error
53 I-Cache Directory Multihit Error
54 D-Cache Directory Multihit Error
55:63

15.3.3 Fault Isolation Register 0 and Associated Registers

The FIRs are implemented as a group of interrelated registers. This section contains register definitions for
FIR0:
• Fault Isolation Register 0 (FIR0)
• FIR0 Action 0 Register (FIR0A0)
• FIR0 Action 1 Register (FIR0A1)
• FIR0 Mask Register (FIR0M)
• FIR0 and FIR1 Register Read (FIR01RD)
Version 1.3
October 23, 2012
Initial
Function
Value
0
Reserved 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved 0
Thread select bits associated with injected error signal.
0 Error signal activated for thread 0.
1 Error signal activated for thread 1.
2 Error signal activated for thread 2.
3 Error signal activated for thread 3.
Causes an I-cache parity error.
Note: This error is independent of any thread select value.
Causes an I-cache directory parity error.
Note: This error is independent of any thread select value.
Causes a D-cache parity error.
Note: This error is independent of any thread select value.
Causes a D-cache directory parity error.
Note: This error is independent of any thread select value.
Causes a parity error in the XU regfile array for the selected thread.
Causes a parity error in the FU regfile array for the selected thread.
Causes an ECC error in the SPRG array for the selected thread.
Causes an ECC error in the inbox array.
Note: This error is independent of any thread select value.
Causes an ECC error in the outbox array.
Note: This error is independent of any thread select value.
Livelock buster logic is activated for the selected thread
Livelock buster logic is active and fails to free up the hang condition
Causes a WDT reset error to occur for the selected thread.
Forces a parity error on a SCOM register write.
Note: This error is independent of any thread select value.
Causes an I-cache directory multihit error.
Note: This error is independent of any thread select value.
Causes a D-cache directory multihit error.
Note: This error is independent of any thread select value.
User's Manual
A2 Processor
Description
SCOM Accessible Registers
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