IBM A2 User Manual page 349

User's Manual
A2 Processor
Programming Note: If ICMP debug events are enabled and debug interrupts (previously disabled) are sub-
sequently enabled, the ICMP debug interrupt occurs sometime after the instruction that enabled the debug
interrupt or on the instruction directly following a context synchronizing event. If the instruction that enabled
the debug interrupt was a context synchronizing instruction, the ICMP debug interrupt occurs on the next
instruction.
Interrupt (IRPT) Exception
An IRPT debug exception occurs when IRPT debug events are enabled (DBCR0[IRPT] = 1) and a base class
interrupt occurs.
Unconditional Debug Event (UDE) Exception
A UDE debug exception occurs when an unconditional debug event is signaled over the JTAG interface to
the A2 core. This exception can occur regardless of debug mode and regardless of the value of MSR[DE].
Instruction Value Compare (IVC) Exception
An IVC debug exception occurs when IVC events are enabled (DBCR3[IVC] = 1) and execution is attempted
of an instruction that matches the following expression:
(IMMR[MASK] & instruction_opcode) = (IMMR[MASK] & IMR[MATCH])
This exception can occur regardless of debug mode, and regardless of the value of MSR[DE].
There are two debug modes supported by the A2 core: internal debug mode and external debug mode.
Debug exceptions and interrupts are affected by the debug modes that are enabled at the time of the debug
exception. Debug interrupts occur only when internal debug mode is enabled, although it is possible for
external debug mode to be enabled as well. The remainder of this section assumes that internal debug mode
is enabled and that external debug mode is not enabled at the time of a debug exception.
See Debug Facilities on page 399 for more information about the different debug modes and the behavior of
each of the Debug exception types when operating in each of the modes.
Programming Note: It is a programming error for software to enable internal debug mode (by setting
DBCR0[IDM] to 1) while debug exceptions are already present in the DBSR. Software must first clear all
DBSR debug exception status fields (that is, all fields except IDE, MRR) before setting DBCR0[IDM] to 1.
A DAC or DVC debug exception occurs regardless of whether a stwcx. or stdcx. would have performed its
store. The CR[CR0] is not updated.
If a DAC exception occurs on an lswx or stswx with a length of zero, the instruction is treated as a no-op, the
debug exception is not recorded in the DBSR, and a debug interrupt does not occur.
If a DAC exception occurs on an icbt, dcbt, or dcbtst instruction that is being no-op'ed for some other reason
(either the referenced cache block is in a caching inhibited memory page or a data storage or data TLB miss
exception occurs), then the debug exception is not recorded in the DBSR and a debug interrupt does not
occur. On the other hand, if the icbt, dcbt, or dcbtst instruction is not being no-op'ed for one of these other
reasons, the DAC debug exception does occur and is handled in the same fashion as other DAC debug
exceptions.
Version 1.3 CPU Interrupts and Exceptions
October 23, 2012 Page 349 of 864