IBM A2 User Manual page 159

Table 4-2. Shadow TLB Array Entry Initialization
Resource Field
2
TLBentry[2] EPN
0:51
X
SIZE
V
ThreadID
Class
ExtClass
TID_NZ
TGS
TS
5
TID
6
TLPID
RPN
22:31
RPN
32:51
R,C
WLC
ResvAttr
U[0:3]
W
I
M
G
E
VF
UX
SX
UW
SW
UR
SR
Version 1.3
October 23, 2012
Reset Value
0x0000000000000 Effective page number (matches IVPR(0:51) reset value).
0 Exclusion range enable bit (disabled).
0b0001 Page size selection (set to 4 KB). This field is recoded to a 3-bit field in the
ERAT shadow copies.
1 Valid bit (enabled).
0b1111 Thread sharing mask (shared by all threads).
0b00 Class ID bits.
1 Extended class ID bit (protected "pinned" entry).
0 Translation identifier nonzero bit.
0 Translation guest state.
0 Translation space (IS or DS matching).
0x00 Translation identifier (set to shared process ID).
N/A Translation logical partition identifier.
3
System-dependent Real page number MSBs (4 GB base real address). Reset value is specified
by the boot configuration ring.
4
System-dependent Real page number LSBs (4 KB real page number offset). Reset value is speci-
fied by the boot configuration ring.
0b00 Reference and change bits.
0b00 D-cache way locking class attribute.
0 Reserved page attributes.
3
System-dependent User-definable storage attributes. Reset value is specified by the boot configu-
ration ring.
0 Write-through storage attribute disabled.
1 Caching inhibited storage attribute enabled.
0 Memory coherent storage attribute disabled.
1 Guarded storage attribute enabled.
3
System-dependent Reset value of endian storage attribute is specified by the boot configuration
ring.
0 Virtualization fault disabled.
0 User-mode execution access disabled.
1 Supervisor-mode execution access enabled.
0 User-mode write access disabled.
0 Supervisor-mode write access disabled.
0 User-mode read access disabled.
1 Supervisor-mode read access enabled.
(Sheet 2 of 3)
User's Manual
A2 Processor
Comment
Page 159 of 864
Initialization